User`s guide

CY7C65113C
Document #: 38-08002 Rev. *G Page 14 of 48
General-purpose I/O Ports
Figure 5. Block Diagram of a GPIO Pin
There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface. Each port can be configured as inputs with internal pull-ups,
open drain outputs, or traditional CMOS outputs. The data for each GPIO port is accessible through the data registers. Port data
registers are shown in Figure 6 through Figure , and are set to 1 on reset.
Figure 6. Port 0 Data.
Special care should be taken with any unused GPIO data bits.
An unused GPIO data bit, either a pin on the chip or a port bit
that is not bonded on a particular package, must not be left
floating when the device enters the suspend state. If a GPIO data
bit is left floating, the leakage current caused by the floating bit
may violate the suspend current limitation specified by the USB
Specifications. If a ‘1’ is written to the unused data bit and the
port is configured with open drain outputs, the unused data bit
remains in an indeterminate state. Therefore, if an unused port
bit is programmed in open-drain mode, it must be written with a
‘0.’
Port 0 Data Address 0x00
Bit # 76543210
Bit Name P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
Reset 11111111
Figure 7. Port1 Data
Port 1 Data Address 0x01
Bit # -----210
Bit Name - - - - - P1.2 P1.1 P1.0
Read/Write-----R/WR/WR/W
Reset -----111
GPIO
V
CC
14 kΩ
GPIO
CFG
mode
2-bits
Data
Out
Latch
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Control
Control
Interrupt
Controller
Q1
Q3*
Q2
*Port 0,1: Low I
sink
Data
Interrupt
Latch
OE
Reg_Bit
STRB
Data
In
Latch
(Latch is Transparent)
PIN