CY7C65113C USB Hub with Microcontroller Features ■ Full Speed USB hub with an integrated microcontroller ■ Internal Power-on Reset (POR) ■ 8-bit USB optimized microcontroller ❐ Harvard architecture ❐ 6-MHz external clock source ❐ 12-MHz internal CPU clock ❐ 48-MHz internal hub clock ■ ■ Internal memory ❐ 256 bytes of RAM ❐ 8 KB of PROM ■ Integrated Master/Slave I2C-compatible Controller (100 kHz) enabled through General-purpose I/O (GPIO) pins ■ I/O ports ❐ Two GPIO ports (Port 0 to 2) capable
CY7C65113C Functional Overview The CY7C65113C device is a one-time programmable 8-bit microcontroller with a built-in 12-Mbps USB hub that supports up to four downstream ports. The microcontroller instruction set has been optimized specifically for USB operations, although the microcontrollers can be used for a variety of non-USB embedded applications. GPIO The CY7C65113C has 11 GPIO pins (P0[7:0], P1[2:0]), both rated at 7 mA per pin (typical) sink current.
CY7C65113C Logic Block Diagram 6-MHz crystal USB Transceiver D+[0] Upstream D–[0] USB Port Downstream USB Ports PLL 48 MHz Clock Divider 12-MHz 8-bit CPU 12 MHz USB Transceiver D+[1] D–[1] USB Transceiver D+[2] D–[2] USB Transceiver D+[3] D–[3] USB Transceiver D+[4] D–[4] Repeater USB SIE RAM 256 byte 8-bit Bus PROM 8 KB Interrupt Controller 6 MHz Power management under firmware control using GPIO pins 12-bit Timer Watchdog Timer GPIO PORT 0 P0[0] GPIO PORT 1 P1[0] I2C comp.
CY7C65113C Contents Pin Configurations ........................................................... 5 Product Summary Tables ................................................ 5 Programming Model ......................................................... 8 Clocking .......................................................................... 11 Reset ................................................................................ 12 Suspend Mode ................................................................
CY7C65113C Pin Configurations Figure 1. CY7C65113C 28-Pin SOIC Top View XTALOUT 1 28 VCC XTALIN 2 27 P1[1] VREF 3 26 P1[0] GND 4 25 P1[2] D+[0] 5 24 D–[3] D–[0] 6 23 D+[3] D+[1] 7 22 D–[4] D–[1] 8 21 D+[4] D+[2] 9 20 GND D–[2] 10 19 VPP P0[7] 11 18 P0[0] P0[5] 12 17 P0[2] P0[3] 13 16 P0[4] P0[1] 14 15 P0[6] Product Summary Tables Pin Assignments Table 1.
CY7C65113C I/O Register Summary the specified port. Specifying address 0 (e.g., IOWX 0h) means the I/O register is selected solely by the contents of X. I/O registers are accessed via the I/O Read (IORD) and I/O Write (IOWR, IOWX) instructions. IORD reads data from the selected port into the accumulator. IOWR performs the reverse; it writes data from the accumulator to the selected port.
CY7C65113C Table 2.
CY7C65113C Table 3.
CY7C65113C Program Memory Organization Figure 2. Program Memory Space with Interrupt Vector Table after reset 14-bit PC Address 0x0000 Program execution begins here after a reset 0x0002 USB Bus Reset interrupt vector 0x0004 128-μs timer interrupt vector 0x0006 1.
CY7C65113C 8-bit Accumulator (A) The accumulator is the general-purpose register for the microcontroller. 8-bit Temporary Register (X) The “X” register is available to the firmware for temporary storage of intermediate results. The microcontroller can perform indexed operations based on the value in X. Refer to Section for additional information. 8-bit Program Stack Pointer (PSP) During a reset, the Program Stack Pointer (PSP) is set to 0x00 and “grows” upward from this address.
CY7C65113C 8-bit Data Stack Pointer (DSP) The Data Stack Pointer (DSP) supports PUSH and POP instructions that use the data stack for temporary storage. A PUSH instruction pre-decrements the DSP, then writes data to the memory location addressed by the DSP. A POP instruction reads data from the memory location addressed by the DSP, then post-increments the DSP. During a reset, the DSP is reset to 0x00. A PUSH instruction when DSP equals 0x00 writes data at the top of the data RAM (address 0xFF).
CY7C65113C The XTALIN and XTALOUT are the clock pins to the microcontroller. The user can connect an external oscillator or a crystal to these pins. When using an external crystal, keep PCB traces between the chip leads and crystal as short as possible (less than 2 cm). A 6-MHz fundamental frequency parallel resonant crystal can be connected to these pins to provide a reference frequency for the internal PLL.
CY7C65113C Suspend Mode Watchdog Reset The WDR occurs when the internal Watchdog Timer rolls over. Writing any value to the write-only Watchdog Reset Clear Register (Figure ) clears the timer. The timer rolls over and WDR occurs if it is not cleared within tWATCH of the last clear (see Section for the value of tWATCH). Bit 6 of the Processor Status and Control Register (Figure 17) is set to record this event (the register contents are set to 010X0001 by the WDR).
CY7C65113C General-purpose I/O Ports Figure 5. Block Diagram of a GPIO Pin VCC GPIO CFG mode 2-bits OE Q2 Control Q1 Data Out Latch Internal Data Bus 14 kΩ GPIO PIN Port Write Q3* Data In Latch Port Read STRB (Latch is Transparent) Data Interrupt Latch Control Reg_Bit Interrupt Enable Interrupt Controller *Port 0,1: Low Isink There are 11 GPIO pins (P0[7:0] and P1[2:0]) for the hardware interface.
CY7C65113C GPIO Configuration Port A read from a GPIO port always returns the present state of the voltage at the pin, independent of the settings in the Port Data Registers. During reset, all of the GPIO pins are set to a high-impedance input state. Writing a ‘0’ to a GPIO pin drives the pin LOW. In this state, a ‘0’ is always read on that GPIO pin unless an external source overdrives the internal pull-down device.
CY7C65113C Table 4. GPIO Port Output Control Truth Table and Interrupt Polarity Port Config Bit 1 Port Config Bit 0 Data Register Output Drive Strength Interrupt Enable Bit 1 0 Output LOW 0 Disabled 1 0 1 Resistive 1 – (Falling Edge) 0 Output LOW 0 Disabled 1 Output HIGH 1 Disabled 0 1 0 Output LOW 0 Disabled 1 Hi-Z 1 – (Falling Edge) 0 0 0 Output LOW 0 Disabled 1 Hi-Z 1 + (Rising Edge) Q1, Q2, and Q3 discussed below are the transistors referenced in Figure .
CY7C65113C 12-bit Free-Running Timer The 12-bit timer operates with a 1-μs tick, provides two interrupts (128 μs and 1.024 ms) and allows the firmware to directly time events that are up to 4 ms in duration. The lower eight bits of the timer can be read directly by the firmware. Reading the lower eight bits latches the upper four bits into a temporary register. When the firmware reads the upper four bits of the timer, it is actually reading the count stored in the temporary register.
CY7C65113C I2C Configuration Register Internal hardware supports communication with external devices through an I2C-compatible interface. I2C-compatible function is discussed in detail in Section .[3] The I2C Position bit (Bit 7, Figure 14) and I2C Port Width bit (Bit 1, Figure 14) select the locations of the SCL (clock) and SDA (data) pins on Port 1 as shown in Table 5. These bits are cleared on reset. When the GPIO is configured for I2C function, the internal pull ups on the pins are disabled.
CY7C65113C Bits [7..0]: I2C Data Contains the 8-bit data on the I2C Bus Figure 16. I2C Status and Control Register. I2C Status and Control Bit # Address 0x28 7 Bit Name 6 MSTR Mode Continue/Bu sy Read/Write 5 4 3 2 1 0 Xmit Mode ACK Addr ARB Lost/Restart Received Stop I2C Enable R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Reset The I2C Status and Control register bits are defined in Table 6, with a more detailed description following. Table 6.
CY7C65113C This bit is valid as a status bit (ARB Lost) after master mode transactions. In master mode, set this bit (along with the Continue and MSTR Mode bits) to perform an I2C restart sequence. The I2C target address for the restart must be written to the data register before setting the Continue bit. To prevent false ARB Lost signals, the Restart bit is cleared by hardware during the restart sequence. start bits, as these cases always cause transmit mode for the first byte.
CY7C65113C before 8 ms. If a WDR occurs during the power-up suspend interval, firmware reads 01010001 from the Status and Control Register after power-up. Normally, the POR bit should be cleared so a subsequent WDR can be clearly identified. If an upstream bus reset is received before firmware examines this register, the Bus Reset bit may also be set. is defined as the condition in which both the D+ line and the D– line are LOW at the same time.
CY7C65113C Bit 0: EPA0 Interrupt Enable 1 = Enable Interrupt on data activity through endpoint A0; 0 = Disable Interrupt on data activity through endpoint A0 Bit 1: EPA1 Interrupt Enable 1 = Enable Interrupt on data activity through endpoint A1; 0 = Disable Interrupt on data activity through endpoint A1 Bit 2: EPA2 Interrupt Enable 1 = Enable Interrupt on data activity through endpoint A2; 0 = Disable Interrupt on data activity through endpoint A2.
CY7C65113C Interrupt Vectors The Interrupt Vectors supported by the USB Controller are listed in Table 7. The lowest-numbered interrupt (USB Bus Reset interrupt) has the highest priority, and the highest-numbered interrupt (I2C interrupt) has the lowest priority. Figure 20.
CY7C65113C Interrupt Latency Interrupt latency can be calculated from the following equation: Interrupt latency = (Number of clock cycles remaining in the current instruction) + (5 clock cycles for the JMP instruction) For example, if a 5-clock cycle instruction such as JC is being executed when an interrupt occurs, the first instruction of the Interrupt Service Routine executes a minimum of 16 clocks (1+10+5) or a maximum of 20 clocks (5+10+5) after the interrupt is issued.
CY7C65113C Figure 21. GPIO Interrupt Structure . Port Configuration Register M U X GPIO Pin 1 = Enable 0 = Disable OR Gate (1 input per GPIO pin) GPIO Interrupt Flip Flop 1 D Q Interrupt Priority Encoder IRQout Interrupt Vector CLR Port Interrupt Enable Register IRA 1 = Enable 0 = Disable Global GPIO Interrupt Enable (Bit 5, Register 0x20) Refer to Sections and for more information of setting GPIO interrupt polarity and enabling individual GPIO interrupts.
CY7C65113C USB Overview The USB hardware includes a USB Hub repeater with one upstream and up to seven downstream ports. The USB Hub repeater interfaces to the microcontroller through a full-speed serial interface engine (SIE). An external series resistor of Rext must be placed in series with all upstream and downstream USB outputs in order to meet the USB driver requirements of the USB specification.
CY7C65113C Connects are recorded by the time a non-SE0 state lasts for more than 2.5 μs on a downstream port. state. The hub repeater recognizes a disconnect once the SE0 state on a downstream port lasts from 2.0 to 2.5 μs. On a disconnect, the corresponding bit in the Hub Ports Connect Status register is cleared, and the Hub Interrupt is generated. When a USB device is disconnected from the Hub, the downstream signal pair eventually floats to a single-ended zero Figure 22. Hub Ports Connect Status .
CY7C65113C defined in Table 8 below. The Hub Downstream Ports Control Register is cleared upon reset or bus reset, and the reset state is the state for normal USB traffic. Any downstream port being forced must be marked as disabled (Figure 24) for proper operation of the hub repeater. Bit [0..3]: Port x Enable (where x = 1..4) Set to 1 if Port x is enabled; Set to 0 if Port x is disabled Bit [4..7]: Reserved. Set to 0.
CY7C65113C The data state of downstream ports can be read through the HUB Ports SE0 Status Register (Figure 27) and the Hub Ports Data Register (Figure 28). The data read from the Hub Ports Data Register is the differential data only and is independent of the settings of the Hub Ports Speed Register (Figure ). When the SE0 condition is sensed on a downstream port, the corresponding bits of the Hub Ports Data Register hold the last differential data state before the SE0.
CY7C65113C Figure 29. Hub Ports Suspend Register Hub Ports Suspend Bit # 7 Bit Name Device Remote Wakeup Read/Write R/W Reset 0 6 Reserved 5 Reserved 4 Reserved R/W 0 R/W 0 R/W 0 3 Port 4 Selective Suspend R/W 0 2 Port 3 Selective Suspend R/W 0 1 Port 2 Selective Suspend R/W 0 Address 0x4D 0 Port 1 Selective Suspend R/W 0 When set to 1, Enable hardware upstream resume signaling for connect/disconnect events during global resume. Bit [0..3]: Port x Selective Suspend (where x = 1..4).
CY7C65113C Figure 31. USB Status and Control Register. USB Status and Control Bit # 7 Bit Name Endpoint Size Read/Write Reset R/W 0 6 Endpoint Mode 5 D+ Upstream 4 D– Upstream 3 Bus Activity R/W 0 R 0 R 0 R/W 0 2 Control Action Bit 2 R/W 0 1 Control Action Bit 1 R/W 0 Address 0x1F 0 Control Action Bit 0 R/W 0 Bits[2..0]: Control Action Set to control action as per Table 9. The three control bits allow the upstream port to be driven manually by firmware.
CY7C65113C USB Device Endpoints Bits[6..0]: Device Address. Firmware writes this bits during the USB enumeration process to the non-zero address assigned by the USB host. Bit 7: Device Address Enable. Must be set by firmware before the SIE can respond to USB traffic to the Device Address. The CY7C65113C controller supports up to two addresses and five endpoints for communication with the host.
CY7C65113C Because of these hardware locking features, firmware must perform an IORD after an IOWR to an endpoint 0 register. This verifies that the contents have changed as desired, and that the SIE has not updated these values. report the type of token received by the corresponding device address is a SETUP token. Any write to this bit by the CPU will clear it (set it to 0).
CY7C65113C Bits[5..0]: Byte Count. These counter bits indicate the number of data bytes in a transaction. For IN transactions, firmware loads the count with the number of bytes to be transmitted to the host from the endpoint FIFO. Valid values are 0 to 32, inclusive. For OUT or SETUP transactions, the count is updated by hardware to the number of data bytes received, plus two for the CRC bytes. Valid values are 2 to 34, inclusive. Bit 6: Data Valid.
CY7C65113C USB Mode Tables Table 11.
CY7C65113C endpoints reset to the disabled mode (0000). Firmware normally enables the endpoint mode after a SetConfiguration request. The control endpoint has three status bits for identifying the token type received (SETUP, IN, or OUT), but the endpoint must be placed in the correct mode to function as such. Non-control endpoints should not be placed into modes that accept SETUPs.
CY7C65113C . Table 13.
CY7C65113C Table 13.
CY7C65113C Register Summary Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] Default/ Reset Port 0 Data P0.7 P0.6 P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 BBBBBBBB 11111111 Port 1 Data P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 BBBBBBBB 11111111 0x02 Port 2 Data P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 P2.1 P2.0 BBBBBBBB 11111111 0x03 Port 3 Data P3.7 P3.6 P3.5 P3.4 P3.3 P3.2 P3.1 P3.0 BBBBBBBB 11111111 0x04 Port 0 Interrupt Enable P0.7 Intr Enable P0.
CY7C65113C Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/Write/B oth/–[7] Default/ Reset HUB PORT CONTROL, STATUS, SUSPEND RESUME, SE0, FORCE LOW (continued) Address 0x48 Hub Port Connect Status Reserved Reserved Reserved Reserved Port 4 Connect Status Port 3 Connect Status Port 2 Connect Status Port 1 Connect Status BBBBBBBB 00000000 HUB PORT CONTROL, STATUS, SUSPEND RESUME, SE0, FORCE LOW Register Summary 0x49 Hub Port Enable Reserved Reserved Reserved
CY7C65113C Sample Schematic 3.3V Regulator OUT IN GND 2.2 μF USB-A Vbus D– D+ GND Vref 2.2 μF Vref 1.5K (RUUP) USB-B Vbus D– D+ GND 0.01 μF Vbus D0– D0+ Vref Vcc 22x2(Rext) SHELL Optional 0.01 μF 22x8(Rext) D1D1+ 4.7 nF 250 VAC D2XTALO 10M 6.000 MHz D2+ XTALI D3- GND GND Vpp D3+ D4D4+ 15K(x8) (RUDN) POWER MANAGEMENT Absolute Maximum Ratings Storage Temperature ................................. –65°C to +150°C Ambient Temperature with Power Applied........
CY7C65113C Electrical Characteristics fOSC = 6 MHz; Operating Temperature = 0 to 70°C, VCC = 4.0V to 5.25V Parameter Description Conditions Min. Max. Unit 3.15 3.45 V –0.4 0.4 V General VREF Reference Voltage Vpp Programming Voltage (disabled) ICC VCC Operating Current ISB1 Supply Current—Suspend Mode 3.
CY7C65113C Switching Characteristics (fOSC = 6.0 MHz) Parameter Description Min. Max. Unit Clock Source fOSC Clock Rate tcyc Clock Period 6 ±0.25% tCH Clock HIGH time 0.45 tCYC ns tCL Clock LOW time 0.45 tCYC ns 166.25 MHz 167.08 ns [10] USB Full-speed Signaling trfs Transition Rise Time 4 tffs Transition Fall Time trfmfs Rise/Fall Time Matching; (tr/tf) tdratefs Full Speed Date Rate 20 ns 4 20 ns 90 111 % 12 ±0.
CY7C65113C Ordering Information Ordering Code PROM Size Package Type Operating Range CY7C65113C-SXC 8 KB 28-pin SOIC Commercial CY7C65113C-SXCT 8 KB 28-pin SOIC-Tape and Reel Commercial Ordering Code Definitions CY 7 C xx xxxx xx C T T = Tape and Reel, Blank = Standard Temperature Range: C = Commercial Package Code: SX = SOIC Part Number: 113C Family Code: 65 = USB Hubs Technology Code: C = CMOS Marketing Code: 7 = Cypress Products Company ID: CY = Cypress Document #: 38-08002 Rev.
CY7C65113C Package Diagram Figure 36. 28-Pin (300-Mil) Molded SOIC 51-85026 *H Document #: 38-08002 Rev.
CY7C65113C Acronyms Acronym Document Conventions Description CMOS complementary metal oxide semiconductor CPU central processing unit DSP data stack pointer EMI electro magnetic interference GPIO general purpose I/O HID human interface device I2C inter integrated circuit LSB least-significant byte MSB most-significant byte PC program counter PLL phase-locked loop POR power on reset PROM precision power on reset PSP program stack pointer RAM random access memory SIE serial i
CY7C65113C Document History Page Document Title: CY7C65113C USB Hub with Microcontroller Document Number: 38-08002 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 109965 02/22/02 SZV Change from Spec number: 38-00590 to 38-08002 *A 120372 12/17/02 MON Added register bit definitions. Added default bit state of each register. Corrected the Schematic (location of the pull-up on D+). Corrected the Logical Diagram (removed the extra GPIO Port 1). Added register summary.
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