User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 44 of 49
MSB
T
MSU
LSB
T
MHD
T
SCKH
T
MDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
T
SCKL
T
MDO
LSBMSB
Figure 26-8. SPI Master Timing, CPHA = 1
MSB
T
SSU
LSB
T
SHD
T
SCKH
T
SDO1
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
T
SCKL
T
SDO
LSBMSB
T
SSS
T
SSH
Figure 26-9. SPI Slave Timing, CPHA = 1