User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 43 of 49
Figure 26-6. SPI Master Timing, CPHA = 0
MSB
T
MSU
LSB
T
MHD
T
SCKH
T
MDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
(SS is under firmware control in SPI Master mode)
T
SCKL
MSB LSB
MSB
T
SSU
LSB
T
SHD
T
SCKH
T
SDO
SS
SCK (CPOL=0)
SCK (CPOL=1)
MOSI
MISO
T
SCKL
T
SSS
T
SSH
MSB LSB
Figure 26-7. SPI Slave Timing, CPHA = 0