User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 41 of 49
T
SCKH
SPI Clock High Time High for CPOL = 0, Low for CPOL = 1 125 ns
T
SCKL
SPI Clock Low Time Low for CPOL = 0, High for CPOL = 1 125 ns
T
MDO
Master Data Output Time SCK to data valid –25 50 ns
T
MDO1
Master Data Output Time,
First bit with CPHA = 1
Time before leading SCK edge 100 ns
T
MSU
Master Input Data Set-up time 50 ns
T
MHD
Master Input Data Hold time 50 ns
T
SSU
Slave Input Data Set-up Time 50 ns
T
SHD
Slave Input Data Hold Time 50 ns
T
SDO
Slave Data Output Time SCK to data valid 100 ns
T
SDO1
Slave Data Output Time,
First bit with CPHA = 1
Time after SS LOW to data valid 100 ns
T
SSS
Slave Select Set-up Time Before first SCK edge 150 ns
T
SSH
Slave Select Hold Time After last SCK edge 150 ns
26.0 Switching Characteristics (continued)
Parameter Description Conditions Min. Max. Unit
Figure 26-1. Clock Timing
Figure 26-2. USB Data Signal Timing
CLOCK
T
CYC
T
CL
T
CH
90%
10%
90%
10%
D−
D+
T
R
T
F
V
crs
V
oh
V
ol