User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 39 of 49
Note:
11. The 200Ω internal resistance at the VREG pin gives a standard USB pull-up using this value. Alternately, a 1.5 kΩ,5%pull-up from D– to an external 3.3V supply
can be used.
V
OLU
Static Output Low With R
PU
to VREG pin 0.3 V
V
OHZ
Static Output High, idle or suspend R
PD
connected D– to Gnd, R
PU
connected D– to VREG pin
[4]
2.7 3.6 V
V
DI
Differential Input Sensitivity |(D+)–(D–)| 0.2 V
V
CM
Differential Input Common Mode Range 0.8 2.5 V
V
SE
Single Ended Receiver Threshold 0.8 2.0 V
C
IN
Transceiver Capacitance 20 pF
I
LO
Hi-Z State Data Line Leakage 0 V < V
in
<3.3 V (D+ or D– pins) –10 10 µA
R
PU
External Bus Pull-up resistance (D–) 1.3 kΩ ±2% to V
REG
[11]
1.274 1.326 kΩ
R
PD
External Bus Pull-down resistance 15 kΩ ±5% to Gnd 14.25 15.75 kΩ
PS/2 Interface
V
OLP
Static Output Low Isink = 5 mA, SDATA or SCLK pins 0.4 V
R
PS2
Internal PS/2 Pull-up Resistance SDATA, SCLK pins, PS/2 Enabled 3 7 kΩ
General Purpose I/O Interface
R
UP
Pull-up Resistance 8 24 kΩ
V
ICR
Input Threshold Voltage, CMOS mode Low to high edge, Port 0 or 1 40% 60% V
CC
V
ICF
Input Threshold Voltage, CMOS mode High to low edge, Port 0 or 1 35% 55% V
CC
V
HC
Input Hysteresis Voltage, CMOS mode High to low edge, Port 0 or 1 3% 10% V
CC
V
ITTL
Input Threshold Voltage, TTL mode Ports 0, 1, and 2 0.8 2.0 V
V
OL1A
V
OL1B
Output Low Voltage, high drive mode I
OL1
= 50 mA, Ports 0 or 1
[4]
I
OL1
= 25 mA, Ports 0 or 1
[4]
0.8
0.4
V
V
V
OL2
Output Low Voltage, medium drive mode I
OL2
= 8 mA, Ports 0 or 1
[4]
0.4 V
V
OL3
Output Low Voltage, low drive mode I
OL3
= 2 mA, Ports 0 or 1
[4]
0.4 V
V
OH
Output High Voltage, strong drive mode Port 0 or 1, I
OH
= 2 mA
[4]
V
CC
–2 V
R
XIN
Pull-down resistance, XTALIN pin Internal Clock Mode only 50 kΩ
25.0 DC Characteristics FOSC = 6 MHz; Operating Temperature = 0 to 70°C (continued)
Parameter Conditions Min. Max. Unit