User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 34 of 49
The response of the SIE can be summarized as follows:
1. The SIE will only respond to valid transactions, and will ig-
nore non-valid ones.
2. The SIE will generate an interrupt when a valid transaction
is completed or when the FIFO is corrupted. FIFO
corruption occurs during an OUT or SETUP transaction to
a valid internal address, that ends with a non-valid CRC.
3. An incoming Data packet is valid if the count is <
Endpoint
Size + 2 (includes CRC) and passes all error checking;
4. An IN will be ignored by an OUT configured endpoint and
visa versa.
5. The IN and OUT PID status is updated at the end of a
transaction.
6. The SETUP PID status is updated at the beginning of the
Data packet phase.
7. The entire Endpoint 0 mode register and the Count register
are locked to CPU writes at the end of any transaction to
that endpoint in which an ACK is transferred. These
registers are only unlocked by a CPU read of these
registers, and only if that read happens after the transaction
completes. This represents about a 1-µs window in which
the CPU is locked from register writes to these USB
registers. Normally the firmware should perform a register
read at the beginning of the Endpoint ISRs to unlock and
get the mode register information. The interlock on the
Mode and Count registers ensures that the firmware
recognizes the changes that the SIE might have made
during the previous transaction.
Table 22-3. Details of Modes for Differing Traffic Conditions
End Point Mode PID Set End Point Mode
3210
Rcved
Token Count Buffer Dval DTOG DVAL COUNT SETUP IN OUT ACK 3 2 1 0 Response Int
SETUP Packet (if accepting)
See22-1 SETUP <= 10 data valid updates 1 updates 1 UC UC 1 0 0 0 1 ACK yes
See22-1 SETUP > 10 junk x updates updates updates 1 UC UC UC NoChange Ignore yes
See 22-1 SETUP x junk invalid updates 0 updates 1 UC UC UC NoChange Ignore yes
Disabled
0 0 0 0 x x UC x UC UC UC UC UC UC UC NoChange Ignore no
NAK IN/OUT
0 0 0 1 OUT x UC x UC UC UC UC UC 1 UC NoChange NAK yes
0 0 0 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 0 0 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 0 0 1 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
Ignore IN/OUT
0 1 0 0 OUT x UC x UC UC UC UC UC UC UC NoChange Ignore no
0 1 0 0 IN x UC x UC UC UC UC UC UC UC NoChange Ignore no
STALL IN/OUT
0 0 1 1 OUT x UC x UC UC UC UC UC 1 UC NoChange STALL yes
0 0 1 1 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 1 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 0 1 1 IN x UC x UC UC UC UC 1 UC UC NoChange STALL yes
Control Write
ACK OUT/NAK IN
1 0 1 1 OUT <= 10 data valid updates 1 updates UC UC 1 1 0 0 0 1 ACK yes
1 0 1 1 OUT > 10 junk x updates updates updates UC UC 1 UC NoChange Ignore yes
1 0 1 1 OUT x junk invalid updates 0 updates UC UC 1 UC NoChange Ignore yes
1 0 1 1 IN x UC x UC UC UC UC 1 UC UC NoChange NAK yes
NAK OUT/Status IN
1 0 1 0 OUT <= 10 UC valid UC UC UC UC UC 1 UC NoChange NAK yes
1 0 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
1 0 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
1 0 1 0 IN x UC x UC UC UC UC 1 UC 1 NoChange TX 0 Byte yes
Status IN Only
0 1 1 0 OUT <= 10 UC valid UC UC UC UC UC 1 UC 0 0 1 1 STALL yes
0 1 1 0 OUT > 10 UC x UC UC UC UC UC UC UC NoChange Ignore no
0 1 1 0 OUT x UC invalid UC UC UC UC UC UC UC NoChange Ignore no
0 1 1 0 IN x UC x UC UC UC UC 1 UC 1 NoChange TX 0 Byte yes