User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 30 of 49
A USB bus reset is indicated by a single ended zero (SE0)
on the USB D+ and D– pins. The USB Bus Reset interrupt
occurs when the SE0 condition ends. PS/2 activity is indi-
cated by a continuous LOW on the SDATA pin. The PS/2
interrupt occurs as soon as the long LOW state is detected.
During the entire interval of a USB Bus Reset or PS/2 inter-
rupt event, the USB Device Address register is cleared.
The Bus Reset/PS/2 interrupt may occur 128 µs after the
bus condition is removed.
1 = Enable
0 = Disable
Bit [7:3]: Reserved.
Bit [2:1]: EP2,1 Interrupt Enable
There are two non-control endpoint (EP2 and EP1) inter-
rupts. If enabled, a non-control endpoint interrupt is gener-
ated when:
• The USB host writes valid data to an endpoint FIFO.
However, if the endpoint is in ACK OUT modes, an in-
terrupt is generated regardless of data packet validity
(i.e., good CRC). Firmware must check for data validity.
• The device SIE sends a NAK or STALL handshake pack-
et to the USB host during the host attempts to read data
from the endpoint (INs).
• The device receives an ACK handshake after a success-
ful read transaction (IN) from the host.
• The device SIE sends a NAK or STALL handshake pack-
et to the USB host during the host attempts to write data
(OUTs) to the endpoint FIFO.
1 = Enable
0 = Disable
Refer to Table 22-1 for more information.
Bit 0: EP0 Interrupt Enable
If enabled, a control endpoint interrupt is generated when:
• The endpoint 0 mode is set to accept a SETUP token.
• After the SIE sends a 0-byte packet in the status stage
of a control transfer.
• The USB host writes valid data to an endpoint FIFO.
However, if the endpoint is in ACK OUT modes, an in-
terrupt is generated regardless of what data is received.
Firmware must check for data validity.
• The device SIE sends a NAK or STALL handshake pack-
et to the USB host during the host attempts to read data
from the endpoint (INs).
• The device SIE sends a NAK or STALL handshake pack-
et to the USB host during the host attempts to write data
(OUTs) to the endpoint FIFO.
1 = Enable EP0 interrupt
0 = Disable EP0 interrupt
Bit # 76543 2 1 0
Bit Name Reserved EP2
Interrupt
Enable
EP1
Interrupt
Enable
EP0
Interrupt
Enable
Read/Write ----- R/W R/W R/W
Reset 00000 0 0 0
Figure 21-2. Endpoint Interrupt Enable Register
(Address 0x21)