User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
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Document #: 38-08022 Rev. *C Page 25 of 49
19.0 Timer Capture Registers
Four 8-bit capture timer registers provide both rising- and
falling-edge event timing capture on two pins. Capture Timer
A is connected to Pin 0.0, and Capture Timer B is connected
to Pin 0.1. These can be used to mark the time at which a rising
or falling event occurs at the two GPIO pins. Each timer will
capture eight bits of the free-running timer into its Capture
Timer Data Register if a rising or falling edge event that
matches the specified rising or falling edge condition at the pin.
A prescaler allows selection of the capture timer tick size.
Interrupts can be individually enabled for the four capture
registers. A block diagram is shown in Figure 19-1.
The four Capture Timer Data Registers are read-only, and are
shown in Figure 19-2 through Figure 19-5.
Out of the 12-bit free running timer, the 8-bit captured in the
Capture Timer Data Registers are determined by the Prescale
Bit [2:0] in the Capture Timer Configuration Register
(Figure 19-7).
.
Figure 19-1. Capture Timers Block Diagram
Free-running Timer
GPIO
P0.0
11 10 9 8 7 4 3 2 1 0
1 MHz
Clock
Rising
Edge
Detect
Falling
Edge
Detect
Timer A Rising Edge Time
6 5
Timer A Falling Edge Time
Prescaler
GPIO
P0.1
Rising
Edge
Detect
Falling
Edge
Detect
Timer B Rising Edge Time
Timer B Falling Edge Time
8-bit Capture Registers
Capture Timer A Interrupt Request
Capture Timer B Interrupt Request
Capture B Falling Int Enable
Capture B Rising Int Enable
Capture A Falling Int Enable
Capture A Rising Int Enable
Bit 0, Reg 0x44
Bit 1, Reg 0x44
Bit 2, Reg 0x44
Bit 3, Reg 0x44
First Edge Hold
Bit 7, Reg 0x44
Mux
Bit # 76543210
Bit Name Capture A Rising Data
Read/Write RRRRRRRR
Reset 00000000
Figure 19-2. Capture Timer A-Rising, Data Register
(Address 0x40)