User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 24 of 49
18.0 12-bit Free-running Timer
The 12-bit timer operates with a 1-µs tick, provides two inter-
rupts (128-µs and 1.024-ms) and allows the firmware to
directly time events that are up to 4 ms in duration. The lower
eight bits of the timer can be read directly by the firmware.
Reading the lower eight bits latches the upper four bits into a
temporary register. When the firmware reads the upper four
bits of the timer, it is actually reading the count stored in the
temporary register. The effect of this is to ensure a stable 12-bit
timer value can be read, even when the two reads are
separated in time.
Bit [7:0]: Timer lower eight bits
Bit [7:4]: Reserved
Bit [3:0]: Timer upper four bits
Bit # 76543210
Bit Name Timer [7:0]
Read/Write RRRRRRRR
Reset 00000000
Figure 18-1. Timer LSB Register (Address 0x24)
Bit # 76543210
Bit Name Reserved Timer [11:8]
Read/Write ----RRRR
Reset 00000000
Figure 18-2. Timer MSB Register (Address 0x25)
Figure 18-3. Timer Block Diagram
10 9 78
5
6 432
1 MHz clock
1.024-ms interrupt
128-
µs interrupt
To Timer Registers
8
1 011
L1 L0L2L3
D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0