User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 23 of 49
17.5 SPI Interrupt
For SPI, an interrupt request is generated after a byte is
received or transmitted. See Section 21.3 for details on the SPI
interrupt.
17.6 SPI Modes for GPIO Pins
The GPIO pins used for SPI outputs (P0.5–P0.7) contain a
bypass mode, as shown in the GPIO block diagram
(Figure 12-1). Whenever the SPI block is inactive (Mode[5:4]
= 00), the bypass value is 1, which enables normal GPIO
operation. When SPI master or slave modes are activated, the
appropriate bypass signals are driven by the hardware for
outputs, and are held at 1 for inputs. Note that the corre-
sponding data bits in the Port 0 Data Register must be set
to 1 for each pin being used for an SPI output. In addition,
the GPIO modes are not affected by operation of the SPI
block, so each pin must be programmed by firmware to the
desired drive strength mode.
For GPIO pins that are not used for SPI outputs, the SPI
bypass value in Figure 12-1 is always 1, for normal GPIO
operation.
MSB LSB
x
SS
SCK (CPOL = 1)
SCK (CPOL = 0)
MOSI/MISO
MSB LSB
x
MOSI/MISO
Data Capture Strobe
Data Capture Strobe
Interrupt Issued
Interrupt Issued
CPHA = 1:
CPHA = 0:
Figure 17-4. SPI Data Timing
Table 17-1. SPI Pin Assignments
SPI Function GPIO Pin Comment
Slave Select (SS
) P0.4 For Master Mode, Firmware sets SS, may use any GPIO pin.
For Slave Mode, SS
is an active LOW input.
Master Out, Slave In (MOSI) P0.5 Data output for master, data input for slave.
Master In, Slave Out (MISO) P0.6 Data input for master, data output for slave.
SCK P0.7 SPI Clock: Output for master, input for slave.