User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 20 of 49
15.0 USB Regulator Output
The VREG pin provides a regulated output for connecting the
pull-up resistor required for USB operation. For USB, a 1.5-kΩ
resistor is connected between the D– pin and the V
REG
voltage, to indicate low-speed USB operation. Since the
VREG output has an internal series resistance of approxi-
mately 200Ω, the external pull-up resistor required is R
PU
(see
Section 25.0).
The regulator output is placed in a high-impedance state at
reset, and must be enabled by firmware by setting the VREG
Enable bit in the USB Status and Control Register
(Figure 13-1). This simplifies the design of a combination
PS/2-USB device, since the USB pull-up resistor can be left in
place during PS/2 operation without loading the PS/2 line. In
this mode, the V
REG
pin can be used as an input and its state
can be read at port P2.0. Refer to Figure 12-8 for the Port 2
data register. This input has a TTL threshold.
In suspend mode, the regulator is automatically disabled. If
VREG Enable bit is set (Figure 13-1), the VREG pin is pulled
up to V
CC
with an internal 6.2-kΩ resistor. This holds the
proper V
OH
state in suspend mode
Note that enabling the device for USB (by setting the Device
Address Enable bit, Figure 14-1) activates the internal
regulator, even if the VREG Enable bit is cleared to 0. This
insures proper USB signaling in the case where the VREG pin
is used as an input, and an external regulator is provided for
the USB pull-up resistor. This also limits the swing on the D–
and D+ pins to about 1V above the internal regulator voltage,
so the Device Address Enable bit normally should only be set
for USB operating modes.
The regulator output is only designed to provide current for the
USB pull-up resistor. In addition, the output voltage at the
VREG pin is effectively disconnected when the CY7C637xxC
device transmits USB from the internal SIE. This means that
the VREG pin does not provide a stable voltage during
transmits, although this does not affect USB signaling.
16.0 PS/2 Operation
The CY7C637xxC parts are optimized for combination USB or
PS/2 devices, through the following features:
1. USB D+ and D– lines can also be used for PS/2 SCLK and
SDATA pins, respectively. With USB disabled, these lines
can be placed in a high-impedance state that will pull up to
V
CC
. (Disable USB by clearing the Address Enable bit of
the USB Device Address Register, Figure 14-1).
2. An interrupt is provided to indicate a long LOW state on the
SDATA pin. This eliminates the need to poll this pin to check
for PS/2 activity. Refer to Section 21.3 for more details.
3. Internal PS/2 pull-up resistors can be enabled on the SCLK
and SDATA lines, so no GPIO pins are required for this task
(bit 7, USB Status and Control Register, Figure 13-1).
4. The controlled slew rate outputs from these pins apply to
both USB and PS/2 modes to minimize EMI.
5. The state of the SCLK and SDATA pins can be read, and
can be individually driven LOW in an open drain mode. The
pins are read at bits [5:4] of Port 2, and are driven with the
Control Bits [2:0] of the USB Status and Control Register.
6. The V
REG
pin can be placed into a high-impedance state,
so that a USB pull-up resistor on the D–/SDATA pin will not
interfere with PS/2 operation (bit 6, USB Status and Control
Register).
The PS/2 on-chip support circuitry is illustrated in Figure 16-1.
Figure 16-1. Diagram of USB-PS/2 System Connections
D–/SDATA
D+/SCLK
5 kΩ
3.3V
Regulator
5 kΩ
V
CC
USB - PS/2
Driver
1.3 kΩ
VREG
VREG Enable
PS/2 Pull-up
Enable
Port 2.0
On-chip Off-chip
Port 2.5
Port 2.4
200Ω