User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 16 of 49
12.1 Auxiliary Input Port
Port 2 serves as an auxiliary input port as shown in
Figure 12-8. The Port 2 inputs all have TTL input thresholds.
Bit [7:6]: Reserved
Bit [5:4]: D+ (SCLK) and D– (SDATA) States
The state of the D+ and D– pins can be read at Port 2 Data
Register. Performing a read from the port pins returns their
logic values.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit [3:2]: Reserved
Bit 1: P2.1 (Internal Clock Mode Only)
In the Internal Clock mode, the XTALIN pin can serve as a
general purpose input, and its state can be read at Port 2,
Bit 1 (P2.1). See Section 9.1 for more details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
Bit 0: P2.0/VREG Pin State
In PS/2 mode, the VREG
pin can be used as an input and
its state can be read at port P2.0. Section 15.0 for more
details.
1 = Port Pin is logic HIGH
0 = Port Pin is logic LOW
13.0 USB Serial Interface Engine (SIE)
The SIE allows the microcontroller to communicate with the
USB host. The SIE simplifies the interface between the micro-
controller and USB by incorporating hardware that handles the
following USB bus activity independently of the microcon-
troller:
• Translate the encoded received data and format the data to
be transmitted on the bus.
• CRC checking and generation. Flag the microcontroller if
errors exist during transmission.
• Address checking. Ignore the transactions not addressed
to the device.
• Send appropriate ACK/NAK/STALL handshakes.
• Token type identification (SETUP, IN, or OUT). Set the ap-
propriate token bit once a valid token is received.
• Place valid received data in the appropriate endpoint FIFOs.
• Send and update the data toggle bit (Data1/0).
• Bit stuffing/unstuffing.
Firmware is required to handle the rest of the USB interface
with the following tasks:
• Coordinate enumeration by decoding USB device requests.
• Fill and empty the FIFOs.
• Suspend/Resume coordination.
• Verify and select Data toggle values.
13.1 USB Enumeration
A typical USB enumeration sequence is shown below. In this
description, ‘Firmware’ refers to embedded firmware in the
CY7C637xxC controller.
1. The host computer sends a SETUP packet followed by a
DATA packet to USB address 0 requesting the Device de-
scriptor.
2. Firmware decodes the request and retrieves its Device
descriptor from the program memory tables.
3. The host computer performs a control read sequence and
Firmware responds by sending the Device descriptor over
the USB bus, via the on-chip FIFO.
4. After receiving the descriptor, the host sends a SETUP
packet followed by a DATA packet to address 0 assigning
a new USB address to the device.
5. Firmware stores the new address in its USB Device
Address Register after the no-data control sequence
completes.
6. The host sends a request for the Device descriptor using
the new USB address.
7. Firmware decodes the request and retrieves the Device
descriptor from program memory tables.
8. The host performs a control read sequence and Firmware
responds by sending its Device descriptor over the USB
bus.
9. The host generates control reads from the device to request
the Configuration and Report descriptors.
10.Once the device receives a Set Configuration request, its
functions may now be used.
11.Firmware should take appropriate action for Endpoint 1
and/or 2 transactions, which may occur from this point.
Table 12-1. Ports 0 and 1 Output Control Truth Table
Data
Register
Mode1 Mode0 Output Drive
Strength
Input
Threshold
0
00
Hi-Z CMOS
1Hi-ZTTL
0
01
Medium
(8 mA) Sink
CMOS
1 High Drive CMOS
0
10
Low (2 mA)
Sink
CMOS
1 Resistive CMOS
0
11
High (50 mA)
Sink
CMOS
1 High Drive CMOS
Bit # 7 6 5 4 3 2 1 0
Bit
Name
Reserved D+
(SCLK)
State
D–
(SDATA)
State
Reserved P2.1
(Internal
Clock
Mode
Only)
P2.0
VREG
Pin
State
Read/
Write
-- R R -- R R
Reset 00 0 0 00 0 0
Figure 12-8. Port 2 Data Register (Address 0x02)