User`s guide

CY7C63722C
CY7C63723C
CY7C63743C
FOR
FOR
Document #: 38-08022 Rev. *C Page 14 of 49
12.0 General Purpose I/O Ports
Ports 0 and 1 provide up to 16 versatile GPIO pins that can be
read or written (the number of pins depends on package type).
Figure 12-1 shows a diagram of a GPIO port pin.
Port 0 is an 8-bit port; Port 1 contains either 2 bits, P1.1–P1.0
in the CY7C63723C, or all 8 bits, P1.7–P1.0 in the
CY7C63743C parts. Each bit can also be selected as an
interrupt source for the microcontroller, as explained in Section
21.0.
The data for each GPIO pin is accessible through the Port
Data register. Writes to the Port Data register store outgoing
data state for the port pins, while reads from the Port Data
register return the actual logic value on the port pins, not the
Port Data register contents.
Each GPIO pin is configured independently. The driving state
of each GPIO pin is determined by the value written to the pin’s
Data Register and by two associated pin’s Mode0 and Mode1
bits.
The Port 0 Data Register is shown in Figure 12-2, and the Port
1 Data Register is shown in Figure 12-3. The Mode0 and
Mode1 bits for the two GPIO ports are given in Figure 12-4
through Figure 12-7.
Table 11-1. Wake-up Timer Adjust Settings
Adjust Bits [2:0]
(Bits [6:4] in Figure 9-2) Wake-up Time
000 (reset state) 1 * t
WAKE
001 2 * t
WAKE
010 4 * t
WAKE
011 8 * t
WAKE
100 16 * t
WAKE
101 32 * t
WAKE
110 64 * t
WAKE
111 128 * t
WAKE
See Section 26.0 for the value of t
WAKE
GPIO
Pin
V
CC
14 kΩ
GPIO
Mode
Data
Out
Register
Internal
Data Bus
Port Read
Port Write
Interrupt
Enable
Interrupt
Control
To Interrupt
Controller
Q1
Q2
Q3
To Capture Timers (P0.0, P0.1)
and SPI (P0.4–P0.7))
Logic
Interrupt
Polarity
2
Threshold Select
SPI Bypass (P0.5–P0.7 only)
(=1 if SPI inactive, or for non-SPI pins)
(Data Reg must be 1
for SPI outputs)
Figure 12-1. Block Diagram of GPIO Port (one pin shown)