Specifications

the nominal 5VDC rail. Cypress recommends this termination method as an alternative to the method described in the USB
specification, as it yields compatible signal levels and does not require the use of a separate 3V regulator.
In the event that a dual-interface design is being implemented, JP1 is left open, and transistor Q1 is installed to allow
firmware control over the USB pullup resistor via Bit 3 of Port 3. On power-up, port pin 3.3 is high impedance, and resistor
R11 guarantees that Q1 is turned OFF, disconnecting pullup R2 from the rail. Once the firmware determines the type of host
interface to be implemented, it may enable the pullup, or leave it disabled, by controlling Q1 as necessary. In the event that
a PS/2 interface is selected, the device relies on the host’s pullup resistors to terminate the open-collector PS/2 clock and
data lines. No pullups are included in the reference design on the device side of the PS/2 interface.
Figure 1. Row/Column Port Configuration
Figure 1. Hardware Implementation
VCC
VCC
Row i
Row port line
Column port line
Column j