Specifications

Configuration
Bits
Interrupt Bit Polarity
11 X Resistive -
10 0 CMOS
Output
disabled
10 1 CMOS Input disabled
01 X Open Drain -
00 X Open Drain +
Ports 0 to 2 offer low current drive with a typical current sink capability of 7 mA. Port 3 offers higher current drive, with a
typical current sink of 12 mA which can be used to drive LEDs.
Each General Purpose I/O (GPIO) is capable of generating an interrupt to the RISC core. Interrupt polarity is selectable on a
per port basis using the GPIO Configuration Register (see Table 1 above.) Selecting a negative polarity (“-”) will cause falling
edges to trigger an interrupt, while a positive polarity (“+”) selects rising edges as triggers. The interrupt triggered by a GPIO
line is individually enabled by a dedicated bit in the Interrupt Enable Register. All GPIO interrupts are further masked by the
Global GPIO Interrupt Enable Bit in the Global Interrupt Enable Register.
The GPIO Configuration Register is located at I/O address 0x08. The Data Registers are located at I/O addresses 0x00 to
0x03 for Port 0 to Port 3 respectively.
Power-up Mode
The CY7C63413 offers 2 modes of operation after a power-on-reset (POR) event: suspend-on-reset (typical for a USB
application) and run-on-reset (typical for a PS/2 application). The suspend-on-reset mode is selected by attaching a pull-up
resistor (100K to 470K Ω) to Vcc on Bit 7 of GPIO Port 3. The run-on-reset mode is selected by attaching a pull-down resis-
tor (0 to 470K Ω) to ground on Bit 7 of GPIO Port 3. See Figure 5 and Figure 6.
Figure 1. One General Purpose I/O Line
Figure 1. Suspend-On-Reset Mode
Figure 1. Run-On-Reset Mode
VCC
Port 3, Bit 7
Rpullup
100K to 470K OHM
Port 3, Bit 7
Rpulldown
0 to 470K OHM