Specifications

the clock line (corresponding to D+) low while floating the data line (corresponding to D-), for instance, would be
accomplished with a setting of ‘110’ in Control Bits 2~0.
The PS/2 firmware can be be viewed as two layers: an interface layer and a command layer. The interface layer processes
the bit-level transaction management between the host and the keyboard, and the command layer deals with the higher-level
implementation of keyboard commands and responses. All PS/2 timing is generated from the keyboard, which is always the
source of the PS/2 clock signal. Interface-layer transaction timing is based on instruction timing. Due to the high instruction-
processing rate of the CY7C63413, code loops are used to generate the short delays required at the PS/2 bit transaction
level, and an assembler macro , DELAY, has been included to simplify the implementation of these delays. See Figures 24
and 25.
At the transaction level, a byte being received from or transmitted to the host computer is handled essentially without
interruption. This is necessary due to the relatively narrow timing requirements at the bit-level interface of the PS/2. While
the 1.28mS interrupt may be serviced within a PS/2 transaction, the ISR is kept sufficiently short that the overall interface
timing requirements can still be met.
The PS/2 host interface command processor is integrated into the main loop. That is, when the keyboard is not being
scanned, the firmware continually checks to see if the host is attempting to send a command. If so, it invokes the code that
accepts and processes the command, returns any required responses, and returns to the main loop. A complete description
of the PS/2 command set and functional requirements, including the parameter descriptions and the electrical timing
specifications for the PS/2 interface is provided in the IBM document referenced at the beginning of this Application Note.