Datasheet

CY7C1543V18
CY7C1545V18
Document Number: 001-05389 Rev. *H Page 5 of 26
Pin Definitions
Pin Name I/O Pin Description
D
[x:0]
Input-
Synchronous
Data Input Signals. Sampled on the rising edge of K and K clocks
when valid write operations are active
.
CY7C1543V18  D
[17:0]
CY7C1545V18  D
[35:0]
WPS Input-
Synchronous
Write Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D
[x:0]
.
BWS
0
,
BWS
1
,
BWS
2
,
BWS
3
Input-
Synchronous
Byte Write Select 0, 1, 2 and 3  Active LOW.
Sampled on the rising edge of the K and K
clocks when
write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C1543V18  BWS
0
controls D
[8:0]
and BWS
1
controls D
[17:9].
CY7C1545V18  BWS
0
controls D
[8:0]
, BWS
1
controls D
[17:9]
,
BWS
2
controls D
[26:18]
and BWS
3
controls D
[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device
.
A Input-
Synchronous
Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
address inputs are multiplexed for both read and write operations. Internally, the device is organized as
4M x 18 (4 arrays each of 1M x 18) for CY7C1543V18 and 2M x 36 (4 arrays each of 512K x 36) for
CY7C1545V18. Therefore, only 20 address inputs are needed to access the entire memory array of
CY7C1543V18 and 19 address inputs for CY7C1545V18. These inputs are ignored when the appropriate
port is deselected.
Q
[x:0]
Outputs-
Synchronous
Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
data is driven out on the rising edge of the K and K
clocks during read operations. On deselecting the
read port, Q
[x:0]
are automatically tristated.
CY7C1543V18  Q
[17:0]
CY7C1545V18  Q
[35:0]
RPS Input-
Synchronous
Read Port Select Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD Valid output
indicator
Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ
.
K Input-
Clock
Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q
[x:0]
. All accesses are initiated on the rising edge of K.
K
Input-
Clock
Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q
[x:0]
.
CQ Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 22.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K
) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 22.
ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus
impedance. CQ, CQ
and Q
[x:0]
output impedance are set to 0.2 x RQ, where RQ is a resistor connected
between ZQ and ground. Alternately, this pin can be connected directly to V
DDQ
, which enables the
minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.
DOFF
Input DLL Turn Off Active LOW. Connecting this pin to ground turns off the DLL inside the device.The timings
in the DLL turned off operation are different from those listed in this data sheet. For normal operation, this
pin can be connected to a pull up through a 10 K or less pull up resistor. The device behaves in QDR I
mode when the DLL is turned off. In this mode, the device can be operated at a frequency of up to 167
MHz with QDR I timing.
TDO Output TDO for JTAG.
TCK Input TCK Pin for JTAG.
TDI Input TDI Pin for JTAG.
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