Datasheet

CY7C1543V18
CY7C1545V18
Document Number: 001-05389 Rev. *H Page 2 of 26
Contents
Features ..............................................................................1
Configurations ....................................................................1
Functional Description .......................................................1
Selection Guide ..................................................................1
Contents ..............................................................................2
Logic Block Diagram (CY7C1543V18) ..............................3
Logic Block Diagram (CY7C1545V18) ..............................3
Pin Configuration ...............................................................4
165-Ball FBGA (15 x 17 x 1.4 mm) Pinout .................... 4
Pin Definitions ....................................................................5
Functional Overview ..........................................................7
Read Operations ........................................................... 7
Write Operations ........................................................... 7
Byte Write Operations ...................................................7
Concurrent Transactions ...............................................7
Depth Expansion ........................................................... 8
Programmable Impedance ............................................8
Echo Clocks ..................................................................8
Valid Data Indicator (QVLD) ..........................................8
DLL ................................................................................8
Application Example .......................................................... 8
Truth Table .......................................................................... 9
Write Cycle Descriptions ...................................................9
Write Cycle Descriptions .................................................10
IEEE 1149.1 Serial Boundary Scan (JTAG) ....................11
Disabling the JTAG Feature ........................................11
Test Access Port—Test Clock ..................................... 11
Test Mode Select (TMS) .............................................11
Test Data-In (TDI) .......................................................11
Test Data-Out (TDO) ...................................................11
Performing a TAP Reset ............................................. 11
TAP Registers .............................................................11
TAP Instruction Set ..................................................... 11
TAP Controller State Diagram .........................................13
TAP Controller Block Diagram ........................................14
TAP Electrical Characteristics ........................................14
TAP AC Switching Characteristics ................................. 15
TAP Timing and Test Conditions ....................................15
Identification Register Definitions .................................. 16
Scan Register Sizes ......................................................... 16
Instruction Codes ............................................................. 16
Boundary Scan Order ......................................................17
Power Up Sequence in QDR II+ SRAM ........................... 18
Power Up Sequence ...................................................18
DLL Constraints ..........................................................18
Maximum Ratings .............................................................19
Operating Range ..............................................................19
Electrical Characteristics ................................................ 19
DC Electrical Characteristics .......................................19
AC Electrical Characteristics ....................................... 20
Capacitance ...................................................................... 21
Thermal Resistance .........................................................21
Switching Characteristics ...............................................22
Switching Waveforms ......................................................23
Read/Write/Deselect Sequence .................................. 23
Ordering Information ....................................................... 24
Package Diagram ............................................................. 24
Document History Page ................................................... 25
Sales, Solutions, and Legal Information ........................ 26
Worldwide Sales and Design Support .........................26
Products ...................................................................... 26
PSoC Solutions ........................................................... 26
[+] Feedback