Datasheet

ManualsBrandsCypress Semiconductor ManualsComputer equipmentCY7C1543V18

THIS SPEC IS OBSOLETE

Spec No: 001-05389

Spec Title: CY7C1543V18/CY7C1545V18, 72-MBIT QDR (R)

II+ SRAM 4-WORD BURST ARCHITECTURE

(2.0 CYCLE READ LATENCY)

Sunset Owner: Jayasree Nayar (NJY)

Replaced by: None

Summary of content (27 pages)

PAGE 1
THIS SPEC IS OBSOLETE Spec No: 001-05389 Spec Title: CY7C1543V18/CY7C1545V18, 72-MBIT QDR (R) II+ SRAM 4-WORD BURST ARCHITECTURE (2.
PAGE 2
CY7C1543V18 CY7C1545V18 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Features Configurations ■ Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.0 cycles: ■ 375 MHz clock for high bandwidth CY7C1545V18 – 2M x 36 ■ 4-word burst for reducing address bus frequency Functional Description ■ Double Data Rate (DDR) interfaces on both read and write ports (data transferred at 750 MHz) at 375 MHz ■ Available in 2.
PAGE 3
CY7C1543V18 CY7C1545V18 Contents Features .............................................................................. 1 Configurations .................................................................... 1 Functional Description ....................................................... 1 Selection Guide .................................................................. 1 Contents .............................................................................. 2 Logic Block Diagram (CY7C1543V18) .............
PAGE 4
CY7C1543V18 CY7C1545V18 Logic Block Diagram (CY7C1543V18) DOFF Address Register Read Add. Decode Write Reg 1M x 18 Array K CLK Gen. Write Reg 1M x 18 Array K Write Reg 1M x 18 Array Address Register Write Reg 1M x 18 Array A(19:0) 20 18 Write Add. Decode D[17:0] Control Logic 20 A(19:0) RPS Read Data Reg. CQ 72 VREF WPS BWS[1:0] 36 Control Logic Reg. 36 Reg. CQ Reg. 18 18 18 18 18 Q[17:0] QVLD Logic Block Diagram (CY7C1545V18) DOFF Address Register Read Add.
PAGE 5
CY7C1543V18 CY7C1545V18 Pin Configuration The pin configuration for CY7C1543V18 and CY7C1545V18 follow.[2] 165-Ball FBGA (15 x 17 x 1.
PAGE 6
CY7C1543V18 CY7C1545V18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1543V18  D[17:0] CY7C1545V18  D[35:0] WPS InputWrite Port Select Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
PAGE 7
CY7C1543V18 CY7C1545V18 Pin Definitions Pin Name (continued) I/O Pin Description TMS Input TMS Pin for JTAG. NC N/A Not Connected to the Die. Can be tied to any voltage level. NC/144M N/A Not Connected to the Die. Can be tied to any voltage level. NC/288M N/A Not Connected to the Die. Can be tied to any voltage level. VREF VDD VSS VDDQ InputReference Reference Voltage Input. Static input used to set the reference level for HSTL inputs and Outputs and AC measurement points.
PAGE 8
CY7C1543V18 CY7C1545V18 Functional Overview The CY7C1543V18 and CY7C1545V18 are synchronous pipelined burst SRAMs equipped with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
PAGE 9
CY7C1543V18 CY7C1545V18 Depth Expansion Valid Data Indicator (QVLD) The CY7C1543V18 has a port select input for each port. This enables for easy depth expansion. Both port selects are sampled on the rising edge of the positive input clock only (K). Each port select input can deselect the specified port. Deselecting a port does not affect the other port. All pending transactions (read and write) are completed before the device is deselected.
PAGE 10
CY7C1543V18 CY7C1545V18 Truth Table The truth table for CY7C1543V18 and CY7C1545V18 follows.[3, 4, 5, 6, 7, 8] Operation K RPS WPS DQ DQ DQ DQ Write Cycle: L-H Load address on the rising edge of K; input write data on two consecutive K and K rising edges. H[9] L[10] D(A) at K(t + 1)  D(A + 1) at K(t +1)  D(A + 2) at K(t + 2)  D(A + 3) at K(t + 2)  Read Cycle: L-H (2.0 cycle Latency) Load address on the rising edge of K; wait two cycles; read data on two consecutive K and K rising edges.
PAGE 11
CY7C1543V18 CY7C1545V18 Write Cycle Descriptions The write cycle description table for CY7C1545V18 follows. [3, 11] BWS0 BWS1 BWS2 BWS3 K K Comments L L L L L–H – During the data portion of a write sequence, all four bytes (D[35:0]) are written into the device. L L L L – L H H H L–H L H H H – H L H H L–H H L H H – H H L H L–H H H L H – H H H L L–H H H H L – H H H H L–H H H H H – Document Number: 001-05389 Rev.
PAGE 12
CY7C1543V18 CY7C1545V18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V I/O logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 13
CY7C1543V18 CY7C1545V18 IDCODE The IDCODE instruction loads a vendor-specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is supplied a Test-Logic-Reset state.
PAGE 14
CY7C1543V18 CY7C1545V18 TAP Controller State Diagram The state diagram for the TAP controller follows.[12] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 12. The 0/1 next to each state represents the value at TMS at the rising edge of TCK. Document Number: 001-05389 Rev.
PAGE 15
CY7C1543V18 CY7C1545V18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [13, 14, 15] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH =2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH =100 A 1.
PAGE 16
CY7C1543V18 CY7C1545V18 TAP AC Switching Characteristics Over the Operating Range [16, 17] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 50 ns
PAGE 17
CY7C1543V18 CY7C1545V18 Identification Register Definitions Value Instruction Field Description CY7C1543V18 CY7C1545V18 000 000 Cypress Device ID (28:12) 11010010101010100 11010010101100100 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
PAGE 18
CY7C1543V18 CY7C1545V18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 11 10N 39 11D 67 1C 95 3M 12 9P 40 9C 68
PAGE 19
CY7C1543V18 CY7C1545V18 Power Up Sequence in QDR II+ SRAM DLL Constraints QDR II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. During Power Up, when the DOFF is tied HIGH, the DLL gets locked after 2048 cycles of stable clock. ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz.
PAGE 20
CY7C1543V18 CY7C1545V18 Maximum Ratings Neutron Soft Error Immunity Description Test Conditions Typ Max* Unit LSBU Logical Single-Bit Upsets 25°C 320 368 FIT/ Mb LMBU Logical Multi-Bit Upsets 25°C 0 0.01 FIT/ Mb Single Event Latchup 85°C 0 0.1 FIT/ Dev Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Storage Temperature ...............................
PAGE 21
CY7C1543V18 CY7C1545V18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [15] Parameter IDD [22] ISB1 Description VDD Operating Supply Automatic Power Down Current Test Conditions Max Unit x18 1300 mA x36 1370 333 MHz x18 1200 x36 1230 300 MHz x18 1100 x36 1140 Max VDD, 375 MHz Both Ports Deselected, VIN  VIH or VIN  VIL f = fMAX = 1/tCYC, Inputs 333 MHz Static x18 525 x36 410 x18 500 x36 395 300 MHz x18 450 x36 385 VDD =
PAGE 22
CY7C1543V18 CY7C1545V18 Capacitance Tested initially and after any design or process change that may affect these parameters. Parameter Description Test Conditions Max Unit 5 pF CIN Input Capacitance CCLK Clock Input Capacitance 6 pF CO Output Capacitance 7 pF 165 FBGA Package Unit 11.82 °C/W 2.33 °C/W TA = 25C, f = 1 MHz, VDD = 1.8V, VDDQ = 1.5V Thermal Resistance Tested initially and after any design or process change that may affect these parameters.
PAGE 23
CY7C1543V18 CY7C1545V18 Switching Characteristics Over the Operating Range [23, 24] CY Consortium Parameter Parameter Description VDD(Typical) to the First Access [25] tPOWER 375 MHz 333 MHz 300 MHz Min Max Min Max Min Max 1 1 1 tCYC tKHKH K Clock Cycle Time 2.66 8.40 3.0 tKH tKHKL Input Clock (K/K) HIGH 0.4 – 0.4 tKL tKLKH Input Clock (K/K) LOW 0.4 – 0.4 tKHKH tKHKH K Clock Rise to K Clock Rise (rising edge to rising edge) 1.13 – 1.28 – 0.4 – 0.4 – 0.4 8.
PAGE 24
CY7C1543V18 CY7C1545V18 Switching Waveforms Read/Write/Deselect Sequence Figure 5. Waveform for 2.0 Cycle Read Latency[31, 32, 33] NOP 1 READ 2 WRITE 3 READ 4 NOP 6 WRITE 5 7 8 K t KH t CYC t KL t KHKH K RPS t SC tHC t SC t HC WPS A A0 A1 A3 A2 t HD t SA t HA t SD D t HD t SD D10 D11 D12 D13 D30 D31 D32 D33 t QVLD t QVLD QVLD t CLZ Q tDOH t CO Q00 (Read Latency = 2.
PAGE 25
CY7C1543V18 CY7C1545V18 Ordering Information The following table contains only the parts that are currently available. If you do not see what you are looking for, contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
PAGE 26
CY7C1543V18 CY7C1545V18 Document History Page Document Title: CY7C1543V18/CY7C1545V18, 72-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.0 Cycle Read Latency) Document Number: 001-05389 Rev. ECN N0. Submission Date Orig.
PAGE 27
CY7C1541V18, CY7C1556V18 CY7C1543V18, CY7C1545V18 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.