Datasheet

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 9 of 34
Write Operations
Write operations are initiated by asserting WPS active at the
rising edge of the positive input clock (K). On the same K clock
rise the data presented to D
[17:0]
is latched and stored into the
lower 18-bit write data register, provided BWS
[1:0]
are both
asserted active. On the subsequent rising edge of the negative
input clock (K), the address is latched and the information
presented to D
[17:0]
is also stored into the write data register,
provided BWS
[1:0]
are both asserted active. The 36 bits of data
are then written into the memory array at the specified location.
When deselected, the write port ignores all inputs after the
pending write operations are completed.
Byte Write Operations
Byte write operations are supported by the CY7C1512KV18. A
write operation is initiated as described in the Write Operations
section. The bytes that are written are determined by BWS
0
and
BWS
1
, which are sampled with each set of 18-bit data words.
Asserting the appropriate Byte Write Select input during the data
portion of a write latches the data being presented and writes it
into the device. Deasserting the Byte write select input during the
data portion of a write enables the data stored in the device for
that byte to remain unaltered. This feature is used to simplify
read, modify, or write operations to a byte write operation.
Single Clock Mode
The CY7C1512KV18 is used with a single clock that controls
both the input and output registers. In this mode the device
recognizes only a single pair of input clocks (K and K
) that control
both the input and output registers. This operation is identical to
the operation if the device had zero skew between the K/K and
C/C
clocks. All timing parameters remain the same in this mode.
To use this mode of operation, the user must tie C and C
HIGH
at power on. This function is a strap option and not alterable
during device operation.
Concurrent Transactions
The read and write ports on the CY7C1512KV18 operate
completely independently of one another. As each port latches
the address inputs on different clock edges, the user can read or
write to any location, regardless of the transaction on the other
port. The user can start reads and writes in the same clock cycle.
If the ports access the same location at the same time, the SRAM
delivers the most recent information associated with the
specified address location. This includes forwarding data from a
write cycle that was initiated on the previous K clock rise.
Depth Expansion
The CY7C1512KV18 has a port select input for each port. This
enables for easy depth expansion. Both port selects are sampled
on the rising edge of the positive input clock only (K). Each port
select input can deselect the specified port. Deselecting a port
does not affect the other port. All pending transactions (read and
write) are completed before the device is deselected.
Programmable Impedance
An external resistor, RQ, must be connected between the ZQ pin
on the SRAM and V
SS
to enable the SRAM to adjust its output
driver impedance. The value of RQ must be 5X the value of the
intended line impedance driven by the SRAM. The allowable
range of RQ to guarantee impedance matching with a tolerance
of ±15% is between 175  and 350 , with V
DDQ
=1.5 V. The
output impedance is adjusted every 1024 cycles upon power up
to account for drifts in supply voltage and temperature.
Echo Clocks
Echo clocks are provided on the QDR II to simplify data capture
on high speed systems. Two echo clocks are generated by the
QDR II. CQ is referenced with respect to C and CQ is referenced
with respect to C
. These are free running clocks and are
synchronized to the output clock of the QDR II. In the single clock
mode, CQ is generated with respect to K and CQ is generated
with respect to K
. The timing for the echo clocks is shown in
Switching Characteristics on page 25.
PLL
These chips use a PLL that is designed to function between
120 MHz and the specified maximum clock frequency. During
power up, when the DOFF
is tied HIGH, the PLL is locked after
20 s of stable clock. The PLL can also be reset by slowing or
stopping the input clocks K and K for a minimum of 30 ns.
However, it is not necessary to reset the PLL to lock to the
desired frequency. The PLL automatically locks 20 s after a
stable clock is presented. The PLL may be disabled by applying
ground to the DOFF
pin. When the PLL is turned off, the device
behaves in QDR I mode (with one cycle latency and a longer
access time).