Datasheet

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 3 of 34
Logic Block Diagram – CY7C1514KV18
1M x 36 Array
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
D
[35:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
36
20
72
36
BWS
[3:0]
V
REF
Write Add. Decode
Write
Reg
36
A
(19:0)
20
CQ
CQ
DOFF
Q
[35:0]
36
36
Write
Reg
C
C
1M x 36 Array
36