Datasheet

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 27 of 34
Switching Waveforms
Read/Write/Deselect Sequence
Figure 6. Waveform for 2.0 Cycle Read Latency
[36, 37, 38]
K
12
34
58
10
6
7
K
RPS
WPS
A
D
READ READ WRITE WRITEWRITE
NOPREAD
WRITE NOP
9
A0
t
KH
t
KHKH
t
KL
t
CYC
tt
HC
t
SA
t
HA
t
SD
t
HD
SC
t
t
SA
t
HA
t
SD
t
HD
A6A5
A3 A4
A1
A2
D30 D50 D51 D61
D31
D11D10 D60
Q
C
C
DON’T CARE
UNDEFINED
t
CQ
CQ
t
KHCH
t
CO
t
KHCH
t
CLZ
CHZ
t
KH
t
KL
Q00 Q01
Q20
t
KHKH
t
CYC
Q21
Q40
Q41
t
CQD
t
DOH
t
CCQO
t
CQOH
t
CCQO
t
CQOH
t
CQDOH
t
CQH
t
CQHCQH
Notes
36. Q00 refers to output from address A0. Q01 refers to output from the next internal burst address following A0, that is, A0 + 1.
37. Outputs are disabled (High Z) one clock cycle after a NOP.
38. In this example, if address A0 = A1, then data Q00 = D10 and Q01 = D11. Write data is forwarded immediately as read results. This note applies to the whole diagram.