Datasheet
CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 26 of 34
Output Times
t
CO
t
CHQV
C/C clock rise (or K/K in single
clock mode) to data valid
–0.45–0.45–0.45–0.45ns
t
DOH
t
CHQX
Data output hold after output C/C
clock rise (active to active)
–0.45 – –0.45 – –0.45 – –0.45 – ns
t
CCQO
t
CHCQV
C/C clock rise to echo clock valid
–0.45–0.45–0.45–0.45ns
t
CQOH
t
CHCQX
Echo clock hold after C/C clock
rise
–0.45 – –0.45 – –0.45 – –0.45 – ns
t
CQD
t
CQHQV
Echo clock high to data valid – 0.25 – 0.25 – 0.27 – 0.30 ns
t
CQDOH
t
CQHQX
Echo clock high to data invalid –0.25 – –0.25 – –0.27 – –0.30 – ns
t
CQH
t
CQHCQL
Output clock (CQ/CQ) HIGH
[32]
1.18 – 1.25 – 1.40 – 1.75 – ns
t
CQHCQH
t
CQHCQH
CQ clock rise to CQ clock rise
(rising edge to rising edge)
[32]
1.18 – 1.25 – 1.40 – 1.75 – ns
t
CHZ
t
CHQZ
Clock (C/C) rise to High Z (active
to high Z)
[33, 34]
–0.45–0.45–0.45–0.45ns
t
CLZ
t
CHQX1
Clock (C/C) rise to low Z
[33, 34]
–0.45 – –0.45 – –0.45 – –0.45 – ns
PLL Timing
t
KC Var
t
KC Var
Clock phase jitter – 0.20 – 0.20 – 0.20 – 0.20 ns
t
KC lock
t
KC lock
PLL lock time (K, C)
[35]
20–20–20–20–s
t
KC Reset
t
KC Reset
K static to PLL reset 30–30–30–30–ns
Switching Characteristics (continued)
Over the Operating Range
Parameters
[29, 30]
Description
350 MHz 333 MHz 300 MHz 250 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min Max Min Max Min Max Min Max
Notes
32. These parameters are extrapolated from the input timing parameters (t
CYC
/2
– 250 ps, where 250 ps is the internal jitter). These parameters are only guaranteed by
design and are not tested in production.
33. t
CHZ
, t
CLZ
, are specified with a load capacitance of 5 pF as in part (b) of Figure 5 on page 24. Transition is measured 100 mV from steady state voltage.
34. At any voltage and temperature t
CHZ
is less than t
CLZ
and t
CHZ
less than t
CO
.
35. For frequencies 300 MHz or below, the Cypress QDR II devices surpass the QDR consortium specification for PLL lock time (t
KC
lock) of 20 µs (min. spec.) and will
lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version.