Datasheet
CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 25 of 34
Switching Characteristics
Over the Operating Range
Parameters
[29, 30]
Description
350 MHz 333 MHz 300 MHz 250 MHz
Unit
Cypress
Parameter
Consortium
Parameter
Min Max Min Max Min Max Min Max
t
POWER
V
DD
(typical) to the first access
[31]
1–1–1–1–ms
t
CYC
t
KHKH
K clock and C clock cycle time 2.85 8.4 3.0 8.4 3.3 8.4 4.0 8.4 ns
t
KH
t
KHKL
Input clock (K/K; C/C) HIGH 1.14 – 1.20 – 1.32 – 1.6 – ns
t
KL
t
KLKH
Input clock (K/K; C/C) LOW 1.14 – 1.20 – 1.32 – 1.6 – ns
t
KHKH
t
KHKH
K clock rise to K clock rise and C
to C
rise (rising edge to rising
edge)
1.28 – 1.35 – 1.49 – 1.8 – ns
t
KHCH
t
KHCH
K/K clock rise to C/C clock rise
(rising edge to rising edge)
01.2201.3001.450 1.8ns
Setup Times
t
SA
t
AVKH
Address setup to K clock rise 0.3 – 0.3 – 0.3 – 0.35 – ns
t
SC
t
IVKH
Control setup to K clock rise
(RPS
,
WPS
)
0.3 – 0.3 – 0.3 – 0.35 – ns
t
SCDDR
t
IVKH
DDR control setup to clock (K/K)
Rise (BWS
0
, BWS
1
, BWS
2
,
BWS
3
)
0.3 – 0.3 – 0.3 – 0.35 – ns
t
SD
t
DVKH
D
[X:0]
setup to clock (K/K) rise 0.3 – 0.3 – 0.3 – 0.35 – ns
Hold Times
t
HA
t
KHAX
Address hold after K clock rise 0.3 – 0.3 – 0.3 – 0.35 – ns
t
HC
t
KHIX
Control hold after K clock rise
(RPS, WPS)
0.3 – 0.3 – 0.3 – 0.35 – ns
t
HCDDR
t
KHIX
DDR control hold after clock (K/K)
rise (BWS
0
, BWS
1
, BWS
2
, BWS
3
)
0.3 – 0.3 – 0.3 – 0.35 – ns
t
HD
t
KHDX
D
[X:0]
hold after clock (K/K) rise 0.3 – 0.3 – 0.3 – 0.35 – ns
Notes
29. Unless otherwise noted, test conditions are based on signal transition time of 2 V/ns, timing reference levels of 0.75 V, Vref = 0.75 V, RQ = 250 , V
DDQ
= 1.5 V, input
pulse levels of 0.25 V to 1.25 V, and output loading of the specified I
OL
/I
OH
and load capacitance shown in (a) of Figure 5 on page 24.
30. When a part with a maximum frequency above 167 MHz is operating at a lower clock frequency, it requires the input timings of the frequency range in which it is
operated and outputs data with the output timings of that frequency range.
31. This part has a voltage regulator internally; t
POWER
is the time that the power must be supplied above V
DD(minimum)
initially before initiating a read or write operation.