Datasheet

CY7C1525KV18
CY7C1512KV18
CY7C1514KV18
Document Number: 001-00436 Rev. *R Page 2 of 34
Logic Block Diagram – CY7C1525KV18
4M x 9 Array
CLK
A
(21:0)
Gen.
K
K
Control
Logic
Address
Register
D
[8:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
9
22
18
9
BWS
[0]
V
REF
Write Add. Decode
Write
Reg
9
A
(21:0)
22
CQ
CQ
DOFF
Q
[8:0]
9
9
Write
Reg
C
C
4M x 9 Array
9
Logic Block Diagram – CY7C1512KV18
2M x 18 Array
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
D
[17:0]
Read Add. Decode
Read Data Reg.
RPS
WPS
Control
Logic
Address
Register
Reg.
Reg.
Reg.
18
21
36
18
BWS
[1:0]
V
REF
Write Add. Decode
Write
Reg
18
A
(20:0)
21
CQ
CQ
DOFF
Q
[17:0]
18
18
Write
Reg
C
C
2M x 18 Array
18