Datasheet

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Document Number: 001-00437 Rev. *J Page 32 of 33
Document History Page
Document Title: CY7C1516KV18/CY7C1527KV18/CY7C1518KV18/CY7C1520KV18, 72-Mbit DDR II SRAM 2-Word
Burst Architecture
Document Number: 001-00437
Rev. ECN No.
Orig. of
Change
Submission
Date
Description of Change
** 374703 SYT See ECN New Data Sheet
*A 1103864 VKN See ECN Updated I
DD
spec
Updated ordering information table
*B 1699246 VKN/AESA See ECN Converted from Advance Information to Preliminary
*C 1939726 VKN/AESA See ECN Changed PLL lock time from 1024 cycles to 20 μs
Added footnote #19 related to I
DD
Corrected typo in the footnote #23
*D 2606839 VKN/PYRS 11/13/08 Changed JTAG ID [31:29] from 001 to 000,
Updated power up sequence waveform and its description,
Changed Ambient Temperature with Power Applied from “–10°C to +85°C” to
“–55°C to +125°C” in the “Maximum Ratings” on page 20,
Included Thermal Resistance values,
Changed the package size from 15 x 17 x 1.4 mm to 13 x 15 x 1.4 mm.
*E 2681899 VKN/PYRS 04/01/2009 Converted from preliminary to final
Added note on top of the Ordering Information table
Moved to external web
*F 2747635 VKN/AESA 08/03/2009 Included Soft Error Immunity Data
Modified Ordering Information table by including parts that are available and
modified the disclaimer for the Ordering information
*G 2767155 VKN/AESA 09/23/2009 Changed Input Capacitance (C
IN
) from 2 pF to 4 pF
Changed Output Capacitance (C
O
) from 3 pF to 4 pF
Modified Ordering code disclaimer
*H 2870201 NJY 02/01/2010 Added Contents.
No technical updates..
*I 2896003 NJY 03/19/2010 Removed inactive parts from Ordering Information
*J 3216622 NJY 04/05/2011 Template updates.
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