Datasheet

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Document Number: 001-00437 Rev. *J Page 17 of 33
TAP AC Switching Characteristics
Over the Operating Range
[13, 14]
Parameter Description Min Max Unit
t
TCYC
TCK clock cycle time 50 – ns
t
TF
TCK clock frequency – 20 MHz
t
TH
TCK clock HIGH 20 – ns
t
TL
TCK clock LOW 20 – ns
Setup Times
t
TMSS
TMS setup to TCK clock rise 5 – ns
t
TDIS
TDI setup to TCK clock rise 5 – ns
t
CS
Capture setup to TCK rise 5 – ns
Hold Times
t
TMSH
TMS hold after TCK clock rise 5 – ns
t
TDIH
TDI hold after clock rise 5 – ns
t
CH
Capture hold after clock rise 5 – ns
Output Times
t
TDOV
TCK clock LOW to TDO valid – 10 ns
t
TDOX
TCK clock LOW to TDO invalid 0 – ns
TAP Timing and Test Conditions
Figure 2 shows the TAP timing and test conditions.
[14]
Figure 2. TAP Timing and Test Conditions
t
TL
t
TH
(a)
TDO
C
L
= 20 pF
Z
0
= 50 Ω
GND
0.9 V
50 Ω
1.8 V
0 V
ALL INPUT PULSES
0.9 V
Test Clock
Test Mode Select
TCK
TMS
Test Data In
TDI
Test Data Out
t
TCYC
t
TMSH
t
TMSS
t
TDIS
t
TDIH
t
TDOV
t
TDOX
TDO
Notes
13. t
CS
and t
CH
refer to the setup and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions. t
R
/t
F
= 1 ns.
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