Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 3 of 30
Logic Block Diagram (CY7C14181KV18)
Logic Block Diagram (CY7C14201KV18)
Write
Reg
Write
Reg
CLK
A
(20:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
18
36
18
BWS
[1:0]
V
REF
Write Add. Decode
18
21
C
C
18
LD
Control
Burst
Logic
A0
A
(20:1)
R/W
DOFF
1M x 18 Array
1M x 18 Array
20
18
DQ
[17:0]
18
CQ
CQ
Write
Reg
Write
Reg
CLK
A
(19:0)
Gen.
K
K
Control
Logic
Address
Register
Read Add. Decode
Read Data Reg.
R/W
Output
Logic
Reg.
Reg.
Reg.
36
72
36
BWS
[3:0]
V
REF
Write Add. Decode
36
20
C
C
36
LD
Control
Burst
Logic
A0
A
(19:1)
R/W
DOFF
512K x 36 Array
512K x 36 Array
19
36
DQ
[35:0]
36
CQ
CQ
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