Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 29 of 30
Package Diagram
Figure 6. 165-Ball FBGA (13 × 15 × 1.4 mm), 51-85180
A
1
PIN 1 CORNER
15.00±0.10
13.00±0.10
7.00
1.00
Ø0.50 (165X)
Ø0.25 M C A B
Ø0.08 M C
B
A
0.15(4X)
SEATING PLANE
0.53±0.05
0.25 C
0.15 C
PIN 1 CORNER
TOP VIEW
BOTTOM VIEW
2345678910
10.00
14.00
B
C
D
E
F
G
H
J
K
L
M
N
11
1110986754321
P
R
P
R
K
M
N
L
J
H
G
F
E
D
C
B
A
A
15.00±0.10
13.00±0.10
B
C
1.00
5.00
0.36
-0.06
+0.14
1.40 MAX.
SOLDER PAD TYPE : NON-SOLDER MASK DEFINED (NSMD)
NOTES :
PACKAGE WEIGHT : 0.475g
JEDEC REFERENCE : MO-216 / ISSUE E
PACKAGE CODE : BB0AC
51-85180-*C
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