Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 22 of 30
I
DD
[19]
V
DD
Operating Supply V
DD
= Max,
I
OUT
= 0 mA,
f = f
MAX
= 1/t
CYC
333 MHz (x8) 510 mA
(x9) 510
(x18) 520
(x36) 640
300 MHz (x8) 480 mA
(x9) 480
(x18) 490
(x36) 600
250 MHz (x8) 420 mA
(x9) 420
(x18) 430
(x36) 530
200 MHz (x8) 370 mA
(x9) 370
(x18) 380
(x36) 450
167 MHz (x8) 340 mA
(x9) 340
(x18) 340
(x36) 400
Electrical Characteristics (continued)
DC Electrical Characteristics
Over the Operating Range
[12]
Parameter Description Test Conditions Min Typ Max Unit
Note
19. The operation current is calculated with 50% read cycle and 50% write cycle.
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