Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 21 of 30
Maximum Ratings
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Storage Temperature ................................. –65°C to +150°C
Ambient Temperature with Power Applied.. –55°C to +125°C
Supply Voltage on V
DD
Relative to GND........–0.5V to +2.9V
Supply Voltage on V
DDQ
Relative to GND.......–0.5V to +V
DD
DC Applied to Outputs in High-Z .........–0.5V to V
DDQ
+ 0.3V
DC Input Voltage
[11]
............................... –0.5V to V
DD
+ 0.3V
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage (MIL-STD-883, M 3015).... >2001V
Latch up Current..................................................... >200 mA
Operating Range
Range
Ambient
Temperature (T
A
) V
DD
[15]
V
DDQ
[15]
Commercial 0°C to +70°C 1.8 ± 0.1V 1.4V to
V
DD
Industrial –40°C to +85°C
Neutron Soft Error Immunity
Parameter Description
Test
Conditions
Typ Max* Unit
LSBU Logical
Single-Bit
Upsets
25°C 197 216 FIT/
Mb
LMBU Logical
Multi-Bit
Upsets
25°C 0 0.01 FIT/
Mb
SEL Single Event
Latchup
85°C 0 0.1 FIT/
Dev
* No LMBU or SEL events occurred during testing; this column represents a
statistical χ
2
, 95% confidence limit calculation. For more details refer to Appli-
cation Note AN 54908 “Accelerated Neutron SER Testing and Calculation of
Terrestrial Failure Rates”
Electrical Characteristics
DC Electrical Characteristics
Over the Operating Range
[12]
Parameter Description Test Conditions Min Typ Max Unit
V
DD
Power Supply Voltage 1.7 1.8 1.9 V
V
DDQ
I/O Supply Voltage 1.4 1.5 V
DD
V
V
OH
Output HIGH Voltage Note 16 V
DDQ
/2 – 0.12 V
DDQ
/2 + 0.12 V
V
OL
Output LOW Voltage Note 17 V
DDQ
/2 – 0.12 V
DDQ
/2 + 0.12 V
V
OH(LOW)
Output HIGH Voltage I
OH
= −0.1 mA, Nominal Impedance V
DDQ
– 0.2 V
DDQ
V
V
OL(LOW)
Output LOW Voltage I
OL
= 0.1 mA, Nominal Impedance V
SS
0.2 V
V
IH
Input HIGH Voltage V
REF
+ 0.1 V
DDQ
+ 0.3 V
V
IL
Input LOW Voltage –0.3 V
REF
– 0.1 V
I
X
Input Leakage Current GND ≤ V
I
≤ V
DDQ
−5 5 μA
I
OZ
Output Leakage Current GND ≤ V
I
≤ V
DDQ,
Output Disabled −5 5 μA
V
REF
Input Reference Voltage
[18]
Typical Value = 0.75V 0.68 0.75 0.95 V
Notes
15. Power up: assumes a linear ramp from 0V to V
DD
(min) within 200 ms. During this time V
IH
< V
DD
and V
DDQ
< V
DD
.
16. Outputs are impedance controlled. I
OH
= –(V
DDQ
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
17. Outputs are impedance controlled. I
OL
= (V
DDQ
/2)/(RQ/5) for values of 175Ω < RQ < 350Ω.
18. V
REF
(min) = 0.68V or 0.46V
DDQ
, whichever is larger, V
REF
(max) = 0.95V or 0.54V
DDQ
, whichever is smaller.
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