Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 18 of 30
Identification Register Definitions
Instruction Field
Value
Description
CY7C14161KV18 CY7C14271KV18 CY7C14181KV18 CY7C14201KV18
Revision Number
(31:29)
000 000 000 000 Version number.
Cypress Device ID
(28:12)
11010100010000100 11010100010001100 11010100010010100 11010100010100100 Defines the type of
SRAM.
Cypress JEDEC ID
(11:1)
00000110100 00000110100 00000110100 00000110100 Allows unique
identification of
SRAM vendor.
ID Register
Presence (0)
1111Indicates the
presence of an ID
register.
Scan Register Sizes
Register Name Bit Size
Instruction 3
Bypass 1
ID 32
Boundary Scan 109
Instruction Codes
Instruction Code Description
EXTEST 000 Captures the input and output ring contents.
IDCODE 001 Loads the ID register with the vendor ID code and places the register between TDI and TDO.
This operation does not affect SRAM operation.
SAMPLE Z 010 Captures the input and output contents. Places the boundary scan register between TDI and
TDO. Forces all SRAM output drivers to a High-Z state.
RESERVED 011 Do Not Use: This instruction is reserved for future use.
SAMPLE/PRELOAD 100 Captures the input and output ring contents. Places the boundary scan register between TDI
and TDO. Does not affect the SRAM operation.
RESERVED 101 Do Not Use: This instruction is reserved for future use.
RESERVED 110 Do Not Use: This instruction is reserved for future use.
BYPASS 111 Places the bypass register between TDI and TDO. This operation does not affect SRAM
operation.
[+] Feedback