Datasheet
Table Of Contents
- Features
- Configurations
- Functional Description
- Logic Block Diagram (CY7C14161KV18)
- Logic Block Diagram (CY7C14271KV18)
- Logic Block Diagram (CY7C14181KV18)
- Logic Block Diagram (CY7C14201KV18)
- Contents
- Pin Configuration
- Pin Definitions
- Functional Overview
- Application Example
- Truth Table
- Burst Address Table (CY7C14181KV18, CY7C14201KV18)
- Write Cycle Descriptions
- Write Cycle Descriptions
- Write Cycle Descriptions
- IEEE 1149.1 Serial Boundary Scan (JTAG)
- TAP Controller State Diagram
- TAP Controller Block Diagram
- TAP Electrical Characteristics
- TAP AC Switching Characteristics
- TAP Timing and Test Conditions
- Identification Register Definitions
- Scan Register Sizes
- Instruction Codes
- Boundary Scan Order
- Power Up Sequence in DDR II SRAM
- Maximum Ratings
- Operating Range
- Neutron Soft Error Immunity
- Electrical Characteristics
- Capacitance
- Thermal Resistance
- Switching Characteristics
- Switching Waveforms
- Ordering Information
- Package Diagram
- Document History Page
- Sales, Solutions, and Legal Information
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Document Number: 001-58826 Rev. *D Page 12 of 30
Write Cycle Descriptions
The write cycle description table for CY7C14271KV18 follows.
[2, 8]
BWS
0
K K
L L–H – During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
L – L–H During the data portion of a write sequence, the single byte (D
[8:0]
) is written into the device.
H L–H – No data is written into the device during this portion of a write operation.
H – L–H No data is written into the device during this portion of a write operation.
Write Cycle Descriptions
The write cycle description table for CY7C14201KV18 follows.
[2, 8]
BWS
0
BWS
1
BWS
2
BWS
3
K K Comments
LLLLL–H–During the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
LLLL–L–HDuring the data portion of a write sequence, all four bytes (D
[35:0]
) are written into
the device.
L H H H L–H – During the data portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
L H H H – L–H During the data portion of a write sequence, only the lower byte (D
[8:0]
) is written
into the device. D
[35:9]
remains unaltered.
H L H H L–H – During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H L H H – L–H During the data portion of a write sequence, only the byte (D
[17:9]
) is written into
the device. D
[8:0]
and D
[35:18]
remains unaltered.
H H L H L–H – During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H H L H – L–H During the data portion of a write sequence, only the byte (D
[26:18]
) is written into
the device. D
[17:0]
and D
[35:27]
remains unaltered.
H H H L L–H – During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
H H H L – L–H During the data portion of a write sequence, only the byte (D
[35:27]
) is written into
the device. D
[26:0]
remains unaltered.
HHHHL–H–No data is written into the device during this portion of a write operation.
HHHH–L–HNo data is written into the device during this portion of a write operation.
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