Datasheet

36-Mbit DDR II SRAM 2-Word
Burst Architecture
CY7C14161KV18, CY7C14271KV18
CY7C14181KV18, CY7C14201KV18
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document Number: 001-58826 Rev. *D Revised October 20, 2010
Features
■ 36-Mbit Density (4M x 8, 4M x 9, 2M x 18, 1M x 36)
■ 333 MHz Clock for High Bandwidth
■ 2-word Burst for reducing Address Bus Frequency
■ Double Data Rate (DDR) Interfaces
(data transferred at 666 MHz) at 333 MHz
■ Two Input Clocks (K and K) for precise DDR Timing
❐ SRAM uses rising edges only
■ Two Input Clocks for Output Data (C and C) to minimize Clock
Skew and Flight Time mismatches
■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed
Systems
■ Synchronous Internally Self-timed Writes
■ DDR II operates with 1.5 Cycle Read Latency when DOFF is
asserted HIGH
■ Operates similar to DDR-I Device with 1 Cycle Read Latency
when DOFF
is asserted LOW
■ 1.8V Core Power Supply with HSTL Inputs and Outputs
■ Variable Drive HSTL Output Buffers
■ Expanded HSTL Output Voltage (1.4V–V
DD
)
❐ Supports both 1.5V and 1.8V I/O supply
■ Available in 165-Ball FBGA Package (13 x 15 x 1.4 mm)
■ Offered in both Pb-free and non Pb-free Packages
■ JTAG 1149.1 compatible Test Access Port
■ Phase Locked Loop (PLL) for Accurate Data Placement
Configurations
CY7C14161KV18 – 4M x 8
CY7C14271KV18 – 4M x 9
CY7C14181KV18 – 2M x 18
CY7C14201KV18 – 1M x 36
Functional Description
The CY7C14161KV18, CY7C14271KV18, CY7C14181KV18,
and CY7C14201KV18 are 1.8V Synchronous Pipelined SRAM
equipped with DDR II architecture. The DDR II consists of an
SRAM core with advanced synchronous peripheral circuitry and
a 1-bit burst counter. Addresses for read and write are latched
on alternate rising edges of the input (K) clock. Write data is
registered on the rising edges of both K and K
. Read data is
driven on the rising edges of C and C
if provided, or on the rising
edge of K and K
if C/C are not provided. Each address location
is associated with two 8-bit words in the case of
CY7C14161KV18 and two 9-bit words in the case of
CY7C14271KV18 that burst sequentially into or out of the
device. The burst counter always starts with a “0” internally in the
case of CY7C14161KV18 and CY7C14271KV18. On
CY7C14181KV18 and CY7C14201KV18, the burst counter
takes in the least significant bit of the external address and bursts
two 18-bit words in the case of CY7C14181KV18 and two 36-bit
words in the case of CY7C14201KV18 sequentially into or out of
the device.
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ
, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design. Output data clocks (C/C
) enable maximum system
clocking and data synchronization flexibility.
All synchronous inputs pass through input registers controlled by
the K or K
input clocks. All data outputs pass through output
registers controlled by the C or C
(or K or K in a single clock
domain) input clocks. Writes are conducted with on-chip
synchronous self-timed write circuitry.
These devices are down bonded from the 65 nm 72M
QDRII+/DDRII+ devices and hence have the same I
DD
/I
SB1
values and the same JTAG ID code as the equivalent 72M device
options. For details refer to the application note AN53189, 65 nm
Technology Interim QDRII+/DDRII+ SRAM device family
description.
Table 1. Selection Guide
Description 333 MHz 300 MHz 250 MHz 200 MHz 167 MHz Unit
Maximum Operating Frequency 333 300 250 200 167 MHz
Maximum Operating Current x8 510 480 420 370 340 mA
x9 510 480 420 370 340
x18 520 490 430 380 340
x36 640 600 530 450 400
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