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72-Mbit QDR

II SRAM 4-Word

Burst Architecture

CY7C1513JV18

CY7C1515JV18

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document Number: 001-12560 Rev. *F Revised August 24, 2009

Features

■ Separate independent Read and Write Data Ports

❐ Supports concurrent transactions

■ 300 MHz clock for High Bandwidth

■ 4-word Burst for reducing Address Bus Frequency

■ Double Data Rate (DDR) Interfaces on both Read and Write

Ports (data transferred at 600 MHz) at 300 MHz

■ Two Input Clocks (K and K) for precise DDR Timing

❐ SRAM uses rising edges only

■ Two Input Clocks for Output Data (C and C) to minimize Clock

Skew and Flight Time Mismatches

■ Echo Clocks (CQ and CQ) simplify Data Capture in High Speed

Systems

■ Single multiplexed Address Input Bus latches Address Inputs

for Read and Write Ports

■ Separate Port Selects for Depth Expansion

■ Synchronous Internally Self-timed Writes

■ QDR

II operates with 1.5 Cycle Read Latency when the Delay

Lock Loop (DLL) is enabled

■ Operates similar to a QDR I Device with one Cycle Read

Latency in DLL Off Mode

■ Available in x18, and x36 Configurations

■ Full Data Coherency, providing Most Current Data

■ Core V

= 1.8 (± 0.1V); IO V

DDQ

= 1.4V to V

■ Available in 165-ball FBGA Package (15 x 17 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free Packages

■ Variable Drive HSTL Output Buffers

■ JTAG 1149.1 compatible Test Access Port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

CY7C1513JV18 – 4M x 18

CY7C1515JV18 – 2M x 36

Functional Description

The CY7C1513JV18, and CY7C1515JV18 are 1.8V

Synchronous Pipelined SRAMs, equipped with QDR II archi-

tecture. QDR II architecture consists of two separate ports: the

read port and the write port to access the memory array. The

read port has dedicated data outputs to support read operations

and the write port has dedicated data inputs to support write

operations. QDR II architecture has separate data inputs and

data outputs to completely eliminate the need to “turn-around”

the data bus that exists with common I/O devices. Each port is

accessed through a common address bus. Addresses for read

and write addresses are latched on alternate rising edges of the

input (K) clock. Accesses to the QDR II read and write ports are

completely independent of one another. To maximize data

throughput, both read and write ports are equipped with DDR

interfaces. Each address location is associated with four 18-bit

words (CY7C1513JV18), or 36-bit words (CY7C1515JV18) that

burst sequentially into or out of the device. Because data is trans-

ferred into and out of the device on every rising edge of both input

clocks (K and K

and C and C), memory bandwidth is maximized

while simplifying system design by eliminating bus ‘turnarounds’.

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

All synchronous inputs pass through input registers controlled by

the K or K

input clocks. All data outputs pass through output

registers controlled by the C or C

(or K or K in a single clock

domain) input clocks. Writes are conducted with on-chip

synchronous self-timed write circuitry.

Selection Guide

Description 300 MHz 250 MHz 167 MHz Unit

Maximum Operating Frequency 300 250 167 MHz

Maximum Operating Current x18 1115 865 615 mA

x36 1140 1040 725

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Summary of content (24 pages)

PAGE 1
CY7C1513JV18 CY7C1515JV18 72-Mbit QDR® II SRAM 4-Word Burst Architecture Features Configurations ■ Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1513JV18 – 4M x 18 ■ 300 MHz clock for High Bandwidth ■ 4-word Burst for reducing Address Bus Frequency Functional Description ■ Double Data Rate (DDR) Interfaces on both Read and Write Ports (data transferred at 600 MHz) at 300 MHz ■ Two Input Clocks (K and K) for precise DDR Timing ❐ SRAM uses rising edges onl
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CY7C1513JV18 CY7C1515JV18 Logic Block Diagram (CY7C1513JV18) DOFF Address Register Read Add. Decode Write Reg 1M x 18 Array K CLK Gen. Write Reg 1M x 18 Array K Write Reg 1M x 18 Array Address Register Write Reg 1M x 18 Array A(19:0) 20 18 Write Add. Decode D[17:0] Control Logic 20 A(19:0) RPS C Read Data Reg. C CQ 72 VREF WPS BWS[1:0] 36 Control Logic Reg. 36 Reg. CQ Reg. 18 18 18 18 18 Q[17:0] Logic Block Diagram (CY7C1515JV18) DOFF Address Register Read Add.
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CY7C1513JV18 CY7C1515JV18 Pin Configuration The pin configuration for CY7C1513JV18 and CY7C1515JV18 follow. [1] 165-Ball FBGA (15 x 17 x 1.
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CY7C1513JV18 CY7C1515JV18 Pin Definitions Pin Name I/O Pin Description D[x:0] InputData Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active. Synchronous CY7C1513JV18 − D[17:0] CY7C1515JV18 − D[35:0] WPS InputWrite Port Select − Active LOW. Sampled on the rising edge of the K clock. When asserted active, a Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D[x:0].
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CY7C1513JV18 CY7C1515JV18 Pin Definitions Pin Name DOFF (continued) I/O Pin Description Input DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The timings in the DLL turned off operation differs from those listed in this data sheet. For normal operation, this pin is connected to a pull up through a 10 KΩ or less pull up resistor. The device behaves in QDR I mode when the DLL is turned off.
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CY7C1513JV18 CY7C1515JV18 Functional Overview The CY7C1513JV18, CY7C1515JV18 are synchronous pipelined Burst SRAMs with a read port and a write port. The read port is dedicated to read operations and the write port is dedicated to write operations. Data flows into the SRAM through the write port and flows out through the read port. These devices multiplex the address inputs to minimize the number of address pins required.
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CY7C1513JV18 CY7C1515JV18 Concurrent Transactions Programmable Impedance The read and write ports on the CY7C1513JV18 operates completely independently of one another. As each port latches the address inputs on different clock edges, the user can read or write to any location, regardless of the transaction on the other port.
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CY7C1513JV18 CY7C1515JV18 Application Example Figure 1 shows four QDR II used in an application. Figure 1.
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CY7C1513JV18 CY7C1515JV18 Write Cycle Descriptions The write cycle description table for CY7C1513JV18 follows. [2, 10] BWS0 BWS1 K K L L L–H – L L – L H L–H L H – H L L–H H L – H H L–H H H – Comments During the data portion of a write sequence: Both bytes (D[17:0]) are written into the device. L-H During the data portion of a write sequence: Both bytes (D[17:0]) are written into the device.
PAGE 10
CY7C1513JV18 CY7C1515JV18 IEEE 1149.1 Serial Boundary Scan (JTAG) These SRAMs incorporate a serial boundary scan Test Access Port (TAP) in the FBGA package. This part is fully compliant with IEEE Standard #1149.1-2001. The TAP operates using JEDEC standard 1.8V IO logic levels. Disabling the JTAG Feature It is possible to operate the SRAM without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW (VSS) to prevent clocking of the device.
PAGE 11
CY7C1513JV18 CY7C1515JV18 IDCODE The IDCODE instruction loads a vendor specific, 32-bit code into the instruction register. It also places the instruction register between the TDI and TDO pins and shifts the IDCODE out of the device when the TAP controller enters the Shift-DR state. The IDCODE instruction is loaded into the instruction register at power up or whenever the TAP controller is given a Test-Logic-Reset state.
PAGE 12
CY7C1513JV18 CY7C1515JV18 TAP Controller State Diagram The state diagram for the TAP controller follows. [11] 1 TEST-LOGIC RESET 0 0 TEST-LOGIC/ IDLE 1 SELECT DR-SCAN 1 1 SELECT IR-SCAN 0 0 1 1 CAPTURE-DR CAPTURE-IR 0 0 SHIFT-DR 0 SHIFT-IR 1 1 EXIT1-DR 1 EXIT1-IR 0 0 PAUSE-IR 1 0 1 EXIT2-DR 0 EXIT2-IR 1 1 UPDATE-IR UPDATE-DR 1 1 0 PAUSE-DR 0 0 0 1 0 Note 11. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
PAGE 13
CY7C1513JV18 CY7C1515JV18 TAP Controller Block Diagram 0 Bypass Register 2 Selection Circuitry TDI 1 0 Selection Circuitry Instruction Register 31 30 29 . . 2 1 0 1 0 TDO Identification Register 108 . . . . 2 Boundary Scan Register TCK TAP Controller TMS TAP Electrical Characteristics Over the Operating Range [12, 13, 14] Parameter Description Test Conditions Min Max Unit VOH1 Output HIGH Voltage IOH = −2.0 mA 1.4 V VOH2 Output HIGH Voltage IOH = −100 μA 1.
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CY7C1513JV18 CY7C1515JV18 TAP AC Switching Characteristics Over the Operating Range [15, 16] Parameter Description Min Max Unit 20 MHz tTCYC TCK Clock Cycle Time tTF TCK Clock Frequency tTH TCK Clock HIGH 20 ns tTL TCK Clock LOW 20 ns tTMSS TMS Setup to TCK Clock Rise 5 ns tTDIS TDI Setup to TCK Clock Rise 5 ns tCS Capture Setup to TCK Rise 5 ns tTMSH TMS Hold after TCK Clock Rise 5 ns tTDIH TDI Hold after Clock Rise 5 ns tCH Capture Hold after Clock Rise 5 ns 50
PAGE 15
CY7C1513JV18 CY7C1515JV18 Identification Register Definitions Value Instruction Field Description CY7C1513JV18 CY7C1515JV18 000 000 Cypress Device ID (28:12) 11010011011010100 11010011011100100 Cypress JEDEC ID (11:1) 00000110100 00000110100 Allows unique identification of SRAM vendor. ID Register Presence (0) 1 1 Indicates the presence of an ID register. Revision Number (31:29) Version number. Defines the type of SRAM.
PAGE 16
CY7C1513JV18 CY7C1515JV18 Boundary Scan Order Bit # Bump ID Bit # Bump ID Bit # Bump ID Bit # Bump ID 0 6R 28 10G 56 6A 84 1J 1 6P 29 9G 57 5B 85 2J 2 6N 30 11F 58 5A 86 3K 3 7P 31 11G 59 4A 87 3J 4 7N 32 9F 60 5C 88 2K 5 7R 33 10F 61 4B 89 1K 6 8R 34 11E 62 3A 90 2L 7 8P 35 10E 63 2A 91 3L 8 9R 36 10D 64 1A 92 1M 9 11P 37 9E 65 2B 93 1L 10 10P 38 10C 66 3B 94 3N 3M 11 10N 39 11D 67 1C 95 12 9P 40 9C 6
PAGE 17
CY7C1513JV18 CY7C1515JV18 Power Up Sequence in QDR II SRAM DLL Constraints QDR II SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. ■ DLL uses K clock as its synchronizing input. The input must have low phase jitter, which is specified as tKC Var. ■ The DLL functions at frequencies down to 120 MHz. ■ If the input clock is unstable and the DLL is enabled, then the DLL may lock onto an incorrect frequency, causing unstable SRAM behavior.
PAGE 18
CY7C1513JV18 CY7C1515JV18 Maximum Ratings Neutron Soft Error Immunity Exceeding maximum ratings may impair the useful life of the device. These user guidelines are not tested. Parameter Storage Temperature ................................. –65°C to +150°C LSBU Logical Single-Bit Upsets 25°C LMBU Logical Multi-Bit Upsets Single Event Latch up Ambient Temperature with Power Applied.. –55°C to +125°C Supply Voltage on VDD Relative to GND ........–0.5V to +2.9V Supply Voltage on VDDQ Relative to GND..
PAGE 19
CY7C1513JV18 CY7C1515JV18 Electrical Characteristics (continued) DC Electrical Characteristics Over the Operating Range [14] Parameter ISB1 Description Test Conditions Automatic Power Down Current Min Typ Max Unit mA Max VDD, 300 MHz Both Ports Deselected, VIN ≥ VIH or VIN ≤ VIL f = fMAX = 1/tCYC, Inputs 250 MHz Static (x18) 405 (x36) 405 (x18) 380 (x36) 380 167 MHz (x18) 340 (x36) 340 AC Electrical Characteristics Over the Operating Range [13] Parameter Description Test Conditions
PAGE 20
CY7C1513JV18 CY7C1515JV18 Switching Characteristics Over the Operating Range [22] Cypress Consortium Parameter Parameter Description VDD(Typical) to the First Access [24] tPOWER 300 MHz 250 MHz 167 MHz Min Max Min Max Min Max 1 1 1 Unit ms tCYC tKHKH K Clock and C Clock Cycle Time 3.3 8.4 4.0 8.4 6.0 8.4 ns tKH tKHKL Input Clock (K/K; C/C) HIGH 1.32 – 1.6 – 2.4 – ns tKL tKLKH Input Clock (K/K; C/C) LOW 1.32 – 1.6 – 2.
PAGE 21
CY7C1513JV18 CY7C1515JV18 Switching Waveforms Figure 5.
PAGE 22
CY7C1513JV18 CY7C1515JV18 Ordering Information The table below contains only the parts that are currently available. If you don’t see what you are looking for, please contact your local sales representative. For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives and distributors.
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CY7C1513JV18 CY7C1515JV18 Package Diagram Figure 6. 165-Ball FBGA (15 x 17 x 1.40 mm), 51-85195 TOP VIEW PIN 1 CORNER 1 2 3 4 5 6 7 8 9 10 11 BOTTOM VIEW PIN 1 CORNER A Ø0.08 M C B Ø0.25 M C A B +0.14 (165X) -0.06 Ø0.50 C 11 D 10 9 8 7 6 5 4 3 2 1 E A F B G C 1.00 H D J E K F L 17.00±0.10 N P 14.00 G M H J K R 7.00 L M N P 0.15 C 0.35±0.06 0.53±0.05 0.25 C R A 1.00 5.00 10.00 B SEATING PLANE 15.00±0.10 1.40 MAX. 0.36 C 0.
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CY7C1513JV18 CY7C1515JV18 Document History Page Document Title: CY7C1513JV18/CY7C1515JV18, 72-Mbit QDR® II SRAM 4-Word Burst Architecture Document Number: 001-12560 Rev. ECN No. Submission Date ** 808457 See ECN Orig.