Specifications

Chapter 2: Board Components 2–53
Components and Interfaces
August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition
Reference Manual
F2 DDR3E_DQ18 1.5-V SSTL L29 Data bus
F8
DDR3E_DQ19 1.5-V SSTL K30 Data bus
H3
DDR3E_DQ20 1.5-V SSTL G32 Data bus
H8
DDR3E_DQ21 1.5-V SSTL F32 Data bus
G2
DDR3E_DQ22 1.5-V SSTL M30 Data bus
H7
DDR3E_DQ23 1.5-V SSTL H32 Data bus
D7
DDR3E_DQ24 1.5-V SSTL W32 Data bus
C3
DDR3E_DQ25 1.5-V SSTL W31 Data bus
C8
DDR3E_DQ26 1.5-V SSTL V31 Data bus
C2
DDR3E_DQ27 1.5-V SSTL R31 Data bus
A7
DDR3E_DQ28 1.5-V SSTL T29 Data bus
A2
DDR3E_DQ29 1.5-V SSTL U30 Data bus
B8
DDR3E_DQ30 1.5-V SSTL P31 Data bus
A3
DDR3E_DQ31 1.5-V SSTL P30 Data bus
F3
DDR3E_DQS_P0 1.5-V SSTL Y30 Data strobe P byte lane 0
G3
DDR3E_DQS_N0 1.5-V SSTL Y29 Data strobe N byte lane 0
C7
DDR3E_DQS_P1 1.5-V SSTL C31 Data strobe P byte lane 1
B7
DDR3E_DQS_N1 1.5-V SSTL B31 Data strobe N byte lane 1
F3
DDR3E_DQS_P2 1.5-V SSTL J30 Data strobe P byte lane 2
G3
DDR3E_DQS_N2 1.5-V SSTL H30 Data strobe N byte lane 2
C7
DDR3E_DQS_P3 1.5-V SSTL T30 Data strobe P byte lane 3
B7
DDR3E_DQS_N3 1.5-V SSTL R30 Data strobe N byte lane 3
K1
DDR3E_ODT 1.5-V SSTL J24 On-die termination
J3
DDR3E_RASN 1.5-V SSTL G31 Row address select
T2
DDR3E_RSTN 1.5-V SSTL W29 Reset
L3
DDR3E_WEN 1.5-V SSTL K28 Write enable
DDR3 Port F Interface (U29, U36)
N3
DDR3F_A0 1.5-V SSTL F36 Address bus
P7
DDR3F_A1 1.5-V SSTL D37 Address bus
P3
DDR3F_A2 1.5-V SSTL P39 Address bus
N2
DDR3F_A3 1.5-V SSTL H36 Address bus
P8
DDR3F_A4 1.5-V SSTL R36 Address bus
P2
DDR3F_A5 1.5-V SSTL C37 Address bus
R8
DDR3F_A6 1.5-V SSTL G37 Address bus
R2
DDR3F_A7 1.5-V SSTL P38 Address bus
T8
DDR3F_A8 1.5-V SSTL N37 Address bus
R3
DDR3F_A9 1.5-V SSTL P37 Address bus
L7
DDR3F_A10 1.5-V SSTL A37 Address bus
R7
DDR3F_A11 1.5-V SSTL J36 Address bus
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 9 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description