Specifications

2–50 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
B7 DDR3C_DQS_N1 1.5-V SSTL H18 Data strobe N byte lane 1
F3
DDR3C_DQS_P2 1.5-V SSTL G19 Data strobe P byte lane 2
G3
DDR3C_DQS_N2 1.5-V SSTL F19 Data strobe N byte lane 2
C7
DDR3C_DQS_P3 1.5-V SSTL T20 Data strobe P byte lane 3
B7
DDR3C_DQS_N3 1.5-V SSTL T19 Data strobe N byte lane 3
K1
DDR3C_ODT 1.5-V SSTL R22 On-die termination
J3
DDR3C_RASN 1.5-V SSTL F21 Row address select
T2
DDR3C_RSTN 1.5-V SSTL H22 Reset
L3
DDR3C_WEN 1.5-V SSTL E20 Write enable
DDR3 Port D Interface (U27, U34)
N3
DDR3D_A0 1.5-V SSTL F25 Address bus
P7
DDR3D_A1 1.5-V SSTL B25 Address bus
P3
DDR3D_A2 1.5-V SSTL T23 Address bus
N2
DDR3D_A3 1.5-V SSTL E26 Address bus
P8
DDR3D_A4 1.5-V SSTL P24 Address bus
P2
DDR3D_A5 1.5-V SSTL A25 Address bus
R8
DDR3D_A6 1.5-V SSTL C25 Address bus
R2
DDR3D_A7 1.5-V SSTL R24 Address bus
T8
DDR3D_A8 1.5-V SSTL D24 Address bus
R3
DDR3D_A9 1.5-V SSTL T24 Address bus
L7
DDR3D_A10 1.5-V SSTL G23 Address bus
R7
DDR3D_A11 1.5-V SSTL D23 Address bus
N7
DDR3D_A12 1.5-V SSTL C24 Address bus
T3
DDR3D_A13 1.5-V SSTL U23 Address bus
M2
DDR3D_BA0 1.5-V SSTL H25 Bank address bus
N8
DDR3D_BA1 1.5-V SSTL B23 Bank address bus
M3
DDR3D_BA2 1.5-V SSTL G25 Bank address bus
K3
DDR3D_CASN 1.5-V SSTL F24 Column address select
K7
DDR3D_CK_N 1.5-V SSTL K24 Clock input N
J7
DDR3D_CK_P 1.5-V SSTL L23 Clock input P
K9
DDR3D_CKE 1.5-V SSTL U24 Clock enable
L2
DDR3D_CSN 1.5-V SSTL F23 Chip select
E3
DDR3D_DQ0 1.5-V SSTL D29 Data bus
F7
DDR3D_DQ1 1.5-V SSTL A26 Data bus
F2
DDR3D_DQ2 1.5-V SSTL B26 Data bus
F8
DDR3D_DQ3 1.5-V SSTL E29 Data bus
H3
DDR3D_DQ4 1.5-V SSTL B28 Data bus
H8
DDR3D_DQ5 1.5-V SSTL C27 Data bus
G2
DDR3D_DQ6 1.5-V SSTL D27 Data bus
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description