Specifications

2–46 Chapter 2: Board Components
Components and Interfaces
100G Development Kit, Stratix V GX Edition August 2012 Altera Corporation
Reference Manual
A2 DDR3A_DQ13 1.5-V SSTL M11 Data bus
B8
DDR3A_DQ14 1.5-V SSTL H10 Data bus
A3
DDR3A_DQ15 1.5-V SSTL J10 Data bus
E3
DDR3A_DQ16 1.5-V SSTL V11 Data bus
F7
DDR3A_DQ17 1.5-V SSTL R13 Data bus
F2
DDR3A_DQ18 1.5-V SSTL U11 Data bus
F8
DDR3A_DQ19 1.5-V SSTL V12 Data bus
H3
DDR3A_DQ20 1.5-V SSTL N13 Data bus
H8
DDR3A_DQ21 1.5-V SSTL P13 Data bus
G2
DDR3A_DQ22 1.5-V SSTL T13 Data bus
H7
DDR3A_DQ23 1.5-V SSTL T14 Data bus
D7
DDR3A_DQ24 1.5-V SSTL E12 Data bus
C3
DDR3A_DQ25 1.5-V SSTL A11 Data bus
C8
DDR3A_DQ26 1.5-V SSTL B11 Data bus
C2
DDR3A_DQ27 1.5-V SSTL A10 Data bus
A7
DDR3A_DQ28 1.5-V SSTL G11 Data bus
A2
DDR3A_DQ29 1.5-V SSTL F11 Data bus
B8
DDR3A_DQ30 1.5-V SSTL C10 Data bus
A3
DDR3A_DQ31 1.5-V SSTL E11 Data bus
F3
DDR3A_DQS_P0 1.5-V SSTL U9 Data strobe P byte lane 0
G3
DDR3A_DQS_N0 1.5-V SSTL T9 Data strobe N byte lane 0
C7
DDR3A_DQS_P1 1.5-V SSTL K11 Data strobe P byte lane 1
B7
DDR3A_DQS_N1 1.5-V SSTL L11 Data strobe N byte lane 1
F3
DDR3A_DQS_P2 1.5-V SSTL P14 Data strobe P byte lane 2
G3
DDR3A_DQS_N2 1.5-V SSTL N14 Data strobe N byte lane 2
C7
DDR3A_DQS_P3 1.5-V SSTL D12 Data strobe P byte lane 3
B7
DDR3A_DQS_N3 1.5-V SSTL C12 Data strobe N byte lane 3
K1
DDR3A_ODT 1.5-V SSTL K8 On-die termination
J3
DDR3A_RASN 1.5-V SSTL B8 Row address select
T2
DDR3A_RSTN 1.5-V SSTL A7 Reset
L3
DDR3A_WEN 1.5-V SSTL C9 Write enable
DDR3 Port B Interface (U25, U32)
N3
DDR3B_A0 1.5-V SSTL B20 Address bus
P7
DDR3B_A1 1.5-V SSTL M14 Address bus
P3
DDR3B_A2 1.5-V SSTL C22 Address bus
N2
DDR3B_A3 1.5-V SSTL A20 Address bus
P8
DDR3B_A4 1.5-V SSTL U20 Address bus
P2
DDR3B_A5 1.5-V SSTL B14 Address bus
R8
DDR3B_A6 1.5-V SSTL U15 Address bus
Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 11)
Board
Reference
Schematic Signal
Name
I/O Standard
Stratix V GX
Device Pin Number
Description