Specifications

August 2012 Altera Corporation 100G Development Kit, Stratix V GX Edition

Reference Manual

1. Overview

The 100G Development Kit, Stratix

V GX Edition allows you to evaluate the

performance of the Stratix V GX FPGA in a 100G design. This document provides the

detailed pin-out and component reference information required to create FPGA

designs that interface with all components on the board.

f For information about setting up the Stratix V GX 100G development board and using

the included software, refer to the 100G Development Kit, Stratix V GX Edition User

Guide.

General Description

The Stratix V GX 100G development board provides a hardware platform for

evaluating the performance and signal integrity features of the Altera

Stratix V GX

devices. The board features the following major component blocks:

■ Stratix V GX FPGA (5SGXEA7N2F45C2N) in 1932-pin FineLine BGA

(FBGA)

package

■ 622,000 logic elements (LEs)

■ 50-Mbits (Mb) embedded memory

■ 48 transceivers

■ 210 full-duplex LVDS channels

■ 28 phase locked loops (PLLs)

■ 512 18x18-bit multipliers

■ 840 user I/Os

■ 2 PCI Express hard IP blocks

■ MAX

II 324-pin CPLD (EPM2210F324C3N)

■ FPGA configuration

■ MAX

II CPLD and Flash Fast Passive Parallel (FPP) configuration

■ 1-Gigabit (Gb) flash storage for two configuration images (factory and user)

■ On-board USB-Blaster

II for use with the Quartus

II Programmer, Nios

software, and System Console

■ JTAG header for external USB-Blaster

■ Memory

■ Twelve 256-Mb DDR3 SDRAM devices

■ Two 72-Mb QDR II SRAM devices

■ Status and setup elements

■ FPGA clock sources