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MNL-01066-1.1

Reference Manual

100G Development Kit, Stratix V GX Edition

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Summary of content (76 pages)

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00G Development Kit, Stratix V GX Edition Reference Manual 101 Innovation Drive San Jose, CA 95134 www.altera.com MNL-01066-1.
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© 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U.S. Patent and Trademark Office and in other countries. All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www.altera.com/common/legal.html.
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Contents Chapter 1. Overview General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Development Board Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–3 Handling the Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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iv Contents Additional Information Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 How to Contact Altera . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1–1 Typographic Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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1. Overview The 100G Development Kit, Stratix® V GX Edition allows you to evaluate the performance of the Stratix V GX FPGA in a 100G design. This document provides the detailed pin-out and component reference information required to create FPGA designs that interface with all components on the board. f For information about setting up the Stratix V GX 100G development board and using the included software, refer to the 100G Development Kit, Stratix V GX Edition User Guide.
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1–2 Chapter 1: Overview General Description ■ Clock outputs and triggers ■ General user input/output ■ ■ ■ Seven user push buttons ■ Two user DIP switches ■ Eight user LEDs ■ Two-line character LCD ■ Ten configuration status LEDs Components and interfaces ■ 10/100/1000 Ethernet PHY and RJ-45 connector ■ USB 2.
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Chapter 1: Overview Development Board Block Diagram 1–3 Development Board Block Diagram Figure 1–1 shows the block diagram of the Stratix V GX 100G development board. Figure 1–1.
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1–4 100G Development Kit, Stratix V GX Edition Reference Manual Chapter 1: Overview Handling the Board August 2012 Altera Corporation
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2. Board Components Introduction This chapter introduces all the important components on the Stratix V GX 100G development board. Figure 2–1 illustrates major component locations and Table 2–1 provides a brief description of all features of the board. 1 A complete set of schematics, a physical layout database, and GERBER files for the development board reside in the Stratix V GX 100G development kit installation directory.
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2–2 Chapter 2: Board Components Board Overview Board Overview This section provides an overview of the Stratix V GX 100G development board, including an annotated board image and component descriptions. Figure 2–1 provides an overview of the board features. Figure 2–1.
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Chapter 2: Board Components Board Overview 2–3 Table 2–1. Stratix V GX 100G Development Board Components (Part 2 of 4) Board Reference Type Description D1 Power LED Indicates the board power status. D20-D23 Ethernet status LEDs Indicates the Ethernet connection speed as well as transmit or receive activity. D31 Factory POF LED Illuminates when the factory design is being loaded into the FPGA. D32 Load LED Illuminates when the FPGA is being configured.
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2–4 Chapter 2: Board Components Board Overview Table 2–1. Stratix V GX 100G Development Board Components (Part 3 of 4) Board Reference Type Description U20 LVPECL to LVDS buffer 644.53125MHz LVDS clock buffer. U47, U48, U49 Differential to LVDS clock buffer Differential clock buffer (2 to 4) distributed to CMU and dedicated differential clock inputs on the vertical banks of the FPGA. U21 Differential divide-by-4 clock divider Divide-by-4 clock circuit to provide the required clock to CFP.
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Chapter 2: Board Components Board Overview 2–5 Table 2–1. Stratix V GX 100G Development Board Components (Part 4 of 4) Board Reference Type Description J4, J16, J38, J60 Interlaken interface Interlaken interface (24 channels). U50 10/100/1000 Ethernet PHY Marvell 88E1111 triple speed Ethernet PHY.
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2–6 Chapter 2: Board Components Featured Device: Stratix V GX FPGA Featured Device: Stratix V GX FPGA The Stratix V GX 100G development board features the 5SGXEA7N2F45C2N Stratix V GX FPGA device (U38) in a 1932-pin FBGA package. f For more information about the Stratix V GX devices, refer to the Stratix V Device Handbook. Table 2–2 describes the features of the Stratix V GX 5SGXEA7N2F45C2N device. Table 2–2.
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Chapter 2: Board Components Featured Device: Stratix V GX FPGA 2–7 Table 2–4. Stratix V GX I/O Usage Summary (Part 2 of 6) Function I/O Type I/O Count Description REFCLKB_CAP_QL2 2.5-V LVDS input 2 Differential REFCLK input PRGCLK_QL1 2.5-V LVDS input 2 Differential REFCLK input SMA_REFCLK_CAP 2.5-V LVDS input 2 Differential REFCLK input FPGA Global Clocks CLKIN_125 2.5-V LVDS input 2 Global clock CLKIN_50_FPGA 2.5-V LVCMOS input 1 Global clock DDR3A_CLK_IN 2.
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2–8 Chapter 2: Board Components Featured Device: Stratix V GX FPGA Table 2–4. Stratix V GX I/O Usage Summary (Part 3 of 6) Function I/O Type I/O Count Description DDR3_CASN 1.5-V SSTL output 1 DDR3 CAS# DDR3_RSTN 1.5-V SSTL output 1 DDR3 reset DDR3_ODT 1.5-V SSTL output 1 DDR3 on-die termination QDR II SRAM (x36) QDR2A_RZQIN 1.5-V 1 QDR II QDR2A_A[19:0] 1.5-V HSTL output 20 QDR II address QDR2A_Q[35:0] 1.5-V HSTL input 36 QDR II data output QDR2A_D[35:0] 1.
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Chapter 2: Board Components Featured Device: Stratix V GX FPGA 2–9 Table 2–4. Stratix V GX I/O Usage Summary (Part 4 of 6) Function I/O Type I/O Count SFP_TXDISABLE 2.5-V LVCMOS output 1 SFP+ transmitter disable SFP_RATESEL 2.5-V LVCMOS output 1 SFP+ rate select SFP_MOD_PRSNTN 2.5-V LVCMOS input 1 SFP+ module present 2.5-V CMOS input 2 SFP+ module absent SFP_SCL 2.5-V LVCMOS output 1 SFP+ serial two-wire clock SFP_SDA 2.
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2–10 Chapter 2: Board Components Featured Device: Stratix V GX FPGA Table 2–4. Stratix V GX I/O Usage Summary (Part 5 of 6) Function I/O Type I/O Count Description MAX2_CLK 2.5-V LVCMOS output 1 FPGA flash control MAX2_OEN 2.5-V LVCMOS output 1 MAX II output enable MAX2_WEN 2.5-V LVCMOS output 1 MAX II write enable MAX2_CSN 2.5-V LVCMOS output 1 MAX II chip select USB_ADDR[1:0] 1.5-V output 2 USB-Blaster II address USB_CLK 1.5-V output 1 USB-Blaster II clock 1.
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Chapter 2: Board Components MAX II CPLD EPM2210 System Controller 2–11 Table 2–4. Stratix V GX I/O Usage Summary (Part 6 of 6) Function I/O Type I/O Count 2.5-V LVCMOS output 1 LCD write enable ENET_TXD[3:0] 2.5-V LVCMOS output 4 Ethernet transmit RGMII data bus ENET_TX_EN 2.5-V LVCMOS output 1 Ethernet transmit enable ENET_GTX_CLK 2.5-V LVCMOS output 1 Ethernet transmit clock ENET_RXD[3:0] 2.5-V LVCMOS input 4 Ethernet receive RGMII data bus ENET_RX_DV 2.
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2–12 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Figure 2–2 illustrates the MAX II CPLD EPM2210 System Controller's functionality and external circuit connections. Figure 2–2.
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Chapter 2: Board Components MAX II CPLD EPM2210 System Controller 2–13 Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 2 of 5) Board Reference (U59) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Pin Description M3 FACTORY 2.5-V — Push button to load factory image into the FPGA M4 FACTORY_POF 2.5-V — LED to Indicate that factory Programmer Object File (.pof) is loaded into the FPGA V15 FACTORY_REQUEST 1.
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2–14 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 3 of 5) Board Reference (U59) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Pin Description A5 FSM_A13 2.5-V AE29 FSM bus flash address B5 FSM_A14 2.5-V AW22 FSM bus flash address A4 FSM_A15 2.5-V AN36 FSM bus flash address A6 FSM_A16 2.5-V AW9 FSM bus flash address B3 FSM_A17 2.
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Chapter 2: Board Components MAX II CPLD EPM2210 System Controller 2–15 Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 4 of 5) Board Reference (U59) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Pin Description G5 LCD_DATA2 2.5-V AV11 LCD data H3 LCD_DATA3 2.5-V AF31 LCD data G4 LCD_DATA4 2.5-V AE12 LCD data G1 LCD_DATA5 2.5-V BD20 LCD data F6 LCD_DATA6 2.5-V AP31 LCD data G2 LCD_DATA7 2.
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2–16 Chapter 2: Board Components MAX II CPLD EPM2210 System Controller Table 2–5. MAX II CPLD EPM2210 System Controller Device Pin-Out (Part 5 of 5) Board Reference (U59) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Pin Description J15 SI5338_PLL_SCL 2.5-V AT21 Si5338 serial two-wire clock for transceiver PLL J17 SI5338_PLL_SDA 2.5-V AJ19 Si5338 serial two-wire data for transceiver PLL G18 STATUSN_LED 2.
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Chapter 2: Board Components Configuration, Status, and Setup Elements 2–17 Table 2–6 lists the MAX II CPLD EPM2210 System Controller component reference and manufacturing information. Table 2–6. MAX II CPLD EPM2210 System Controller Component Reference and Manufacturing Information Board Reference Description Manufacturer Manufacturing Part Number Manufacturer Website U59 MAX II CPLD EPM2210 324FBGA -3 Altera Corporation EPM2210F324C3N www.altera.
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2–18 Chapter 2: Board Components Configuration, Status, and Setup Elements FPGA Programming from Flash Memory On either power-up or by pressing the LOAD or FACTORY push button (S5 or S6), the MAX II CPLD System Controller’s parallel flash loader configures the FPGA from the flash memory. The configuration program select push-button, PGM_SEL, (S8) selects between two .pof files (factory or user) stored in the flash.
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Chapter 2: Board Components Configuration, Status, and Setup Elements 2–19 Figure 2–5 shows the schematic connections for the dedicated JTAG programming header (J59). Figure 2–5.
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2–20 Chapter 2: Board Components Configuration, Status, and Setup Elements Table 2–7. Status LEDs (Part 2 of 2) Board Reference LED Name Schematic Signal Name I/O Standard LED Description D18 TX ENET_LED_TX Green LED. Blinks to indicate Ethernet PHY 2.5-V CMOS transmit activity. Driven by the Marvell 88E1111 PHY. D19 RX ENET_LED_RX 2.
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Chapter 2: Board Components Configuration, Status, and Setup Elements 2–21 Setup Elements The development board includes several different kinds of setup elements. This section describes the following setup elements: ■ Board settings DIP switch ■ Push buttons ■ Board jumpers Board settings DIP switch The board settings DIP switch (SW3) controls various features specific to the board and the MAX II CPLD EPM2210 System Controller logic design.
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2–22 Chapter 2: Board Components Configuration, Status, and Setup Elements Push Buttons Board reference S1 is the CPU reset push button, CPU_RESET, which is an input to the Stratix V GX device. The CPU_RESET is the master reset signal for the FPGA design loaded into the Stratix V GX device. You must enable the CPU_RESET signal within the Quartus II software for this reset function to work. Otherwise, the CPU_RESET acts as a regular I/O pin.
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Chapter 2: Board Components Clock Circuitry 2–23 Clock Circuitry The clock tree structure for the line side and QDRII interface on the Stratix V GX board is made up of two programmable quad PLLs where each output can be programmed for a specific frequency. The default frequency for the clocks going to QL0 through QL3 is 644.53125 MHz and the default frequency going to the QDRII interface is 100 MHz.
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2–24 Chapter 2: Board Components Clock Circuitry Figure 2–7 shows the Stratix V GX development board clock tree structure for the Interlaken side and DDR3 interface. Figure 2–7.
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Chapter 2: Board Components Clock Circuitry 2–25 Table 2–14. Clock Circuitry Pin-Out (Part 2 of 2) Schematic Signal Name I/O Standard Stratix V GX Device Pin Name Description REFCLK_QR0_N/P LVDS AK39/AK38 Differential programmable clock to reference clock for the transceivers that go to the Interlaken interface. REFCLK_QR1_N/P LVDS AF39/AF38 Differential programmable clock to reference clock for the transceivers that go to the Interlaken interface.
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2–26 Chapter 2: Board Components General User Input/Output General User Input/Output This section describes the user I/O interface to the FPGA and MAX II CPLD EPM2210 System Controller, including the following elements: ■ User push buttons ■ User DIP switches ■ User LEDs ■ LCD Figure 2–8 shows the general user I/O connection. Figure 2–8.
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Chapter 2: Board Components General User Input/Output 2–27 Table 2–15. User Push Button Signal Names and Functions (Part 2 of 2) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number — MAX II user push button S4 USER_PB0 2.5-V CMOS Description S9 FPGA_USER_PB3 2.5-V CMOS AM23 FPGA user push button S10 FPGA_USER_PB2 2.5-V CMOS AW23 FPGA user push button S11 FPGA_USER_PB1 2.5-V CMOS AR24 FPGA user push button S12 FPGA_USER_PB0 2.
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2–28 Chapter 2: Board Components General User Input/Output Table 2–17. User-Defined DIP Switch Schematic Signal Names and Functions Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number AG12 SW4.1 FPGA_USER_DIPSW0 2.5-V CMOS SW4.2 FPGA_USER_DIPSW1 2.5-V CMOS BC7 SW4.3 FPGA_USER_DIPSW2 2.5-V CMOS AE13 SW4.4 FPGA_USER_DIPSW3 2.5-V CMOS AG21 SW4.5 FPGA_USER_DIPSW4 2.5-V CMOS AY22 SW4.6 FPGA_USER_DIPSW5 2.5-V CMOS AU9 SW4.7 FPGA_USER_DIPSW6 2.
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Chapter 2: Board Components General User Input/Output 2–29 Table 2–19. User-Defined LED Schematic Signal Names and Functions (Part 2 of 2) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number D43 FPGA_USER_LED7 2.5-V CMOS AY19 D44 FPGA_USER_LED6 2.5-V CMOS D36 D45 FPGA_USER_LED5 2.5-V CMOS AN17 D46 FPGA_USER_LED4 2.5-V CMOS AV23 D47 FPGA_USER_LED3 2.5-V CMOS AK18 D48 FPGA_USER_LED2 2.5-V CMOS AN14 D49 FPGA_USER_LED1 2.
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2–30 Chapter 2: Board Components Flash Memory Table 2–22 shows the LCD pin definitions, and is an excerpt from the Lumex data sheet. f For more information such as timing, character maps, interface guidelines, and other related documentation, visit www.lumex.com. Table 2–22.
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Chapter 2: Board Components Flash Memory 2–31 Table 2–24. Flash Memory Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference (U60) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number AF14 Flash clock Description E6 FLASH_CLK 2.5-V CMOS F8 FLASH_OEN 2.5-V CMOS AV8 Flash output enable F7 FLASH_RDYBSYN 2.5-V CMOS AU20 Flash ready D4 FLASH_RESETN 2.5-V CMOS AE32 Flash reset G8 FLASH_WEN 2.
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2–32 Chapter 2: Board Components Components and Interfaces Table 2–24. Flash Memory Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference (U60) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number AF13 Flash data bus Description H7 FSM_D7 2.5-V CMOS E1 FSM_D8 2.5-V CMOS AP9 Flash data bus E3 FSM_D9 2.5-V CMOS AJ32 Flash data bus F3 FSM_D10 2.5-V CMOS AT33 Flash data bus F4 FSM_D11 2.5-V CMOS AK9 Flash data bus F5 FSM_D12 2.
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Chapter 2: Board Components Components and Interfaces 2–33 QSFP Interface The development board includes two QSFP interfaces for a 40G QSFP module. The QSFP interface can support four full-duplex transceiver channels. Table 2–26 lists the pin assignments for the first QSFP interface (J33) and their corresponding schematic signal names and Stratix V GX pin numbers. Table 2–26.
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2–34 Chapter 2: Board Components Components and Interfaces Table 2–26. QSFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (J33) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 6 QSFP0_TX_P3 1.5-V PCML AN4 Transmit XCVR pair 3 from FPGA 5 QSFP0_TX_N3 1.
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Chapter 2: Board Components Components and Interfaces 2–35 Table 2–27. QSFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 2) Board Reference (J19) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 2 QSFP1_TX_N1 1.5-V PCML H5 Transmit XCVR pair 1 from FPGA 33 QSFP1_TX_P2 1.5-V PCML G4 Transmit XCVR pair 2 from FPGA 34 QSFP1_TX_N2 1.5-V PCML G3 Transmit XCVR pair 2 from FPGA 6 QSFP1_TX_P3 1.
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2–36 Chapter 2: Board Components Components and Interfaces Table 2–29. SFP+ Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 3) Board Reference (J10) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 62 SFP0_TXFAULT 2.5-V LVCMOS BA9 Interface transmitter fault 48 SFP1_LOS 2.5-V LVCMOS AG13 Signal loss indicator from the SFP+ interface 46 SFP1_MOD0_PRSNTN 2.
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Chapter 2: Board Components Components and Interfaces 2–37 Table 2–29. SFP+ Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 3) Board Reference (J10) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 13 SFP3_RDP 1.5-V PCML C4 Received data (output from the SFP+ interface) 9 SFP3_RS1 2.5-V LVCMOS AG33 19 SFP3_TDN 1.5-V PCML D5 Transmitted data (input to the SFP+ interface) 18 SFP3_TDP 1.
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2–38 Chapter 2: Board Components Components and Interfaces Table 2–31. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 4) Board Reference (J25) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description Programmable alarm 1 set via MDIO and MSA for RXS, RX CDR lock indication. 33 CFP_PRG_ALRM1 2.5-V LVCMOS AG34 0: Locked 1: Unlocked Programmable alarm 2 set via MDIO and MSA (HIPWR_ON). 34 CFP_PRG_ALRM2 2.
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Chapter 2: Board Components Components and Interfaces 2–39 Table 2–31. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 4) Board Reference (J25) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 86 CFP_RX_N2 1.5-V PCML AK1 Receive XCVR pair 2 to FPGA 88 CFP_RX_P3 1.5-V PCML AH2 Receive XCVR pair 3 to FPGA 89 CFP_RX_N3 1.5-V PCML AH1 Receive XCVR pair 3 to FPGA 91 CFP_RX_P4 1.
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2–40 Chapter 2: Board Components Components and Interfaces Table 2–31. CFP Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 4) Board Reference (J25) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 132 CFP_TX_N6 1.5-V PCML U3 Transmit XCVR pair 6 from FPGA 134 CFP_TX_P7 1.5-V PCML R4 Transmit XCVR pair 7 from FPGA 135 CFP_TX_N7 1.5-V PCML R3 Transmit XCVR pair 7 from FPGA 137 CFP_TX_P8 1.
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Chapter 2: Board Components Components and Interfaces 2–41 Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 5) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description D6 INT_TX_P1 1.5-V PCML AG41 Transmit XCVR pair 1 from FPGA E6 INT_TX_N1 1.5-V PCML AG42 Transmit XCVR pair 1 from FPGA D8 INT_TX_P2 1.5-V PCML AC41 Transmit XCVR pair 2 from FPGA E8 INT_TX_N2 1.
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2–42 Chapter 2: Board Components Components and Interfaces Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 5) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description B3 INT_RX_N4 1.5-V PCML AY44 Receive XCVR pair 4 to FPGA D2 INT_RX_P5 1.5-V PCML BB43 Receive XCVR pair 5 to FPGA E2 INT_RX_N5 1.5-V PCML BB44 Receive XCVR pair 5 to FPGA D4 INT_RX_P6 1.
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Chapter 2: Board Components Components and Interfaces 2–43 Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 5) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description E4 INT_TX_N18 1.5-V PCML L42 Transmit XCVR pair 18 from FPGA A5 INT_TX_P19 1.5-V PCML K39 Transmit XCVR pair 19 from FPGA B5 INT_TX_N19 1.5-V PCML K40 Transmit XCVR pair 19 from FPGA G5 INT_TX_P20 1.
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2–44 Chapter 2: Board Components Components and Interfaces Table 2–33. Interlaken Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 5) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description G3 INT_RX_P21 1.5-V PCML T43 Receive XCVR pair 21 to FPGA H3 INT_RX_N21 1.5-V PCML T44 Receive XCVR pair 21 to FPGA J4 INT_RX_P22 1.5-V PCML H43 Receive XCVR pair 22 to FPGA K4 INT_RX_N22 1.
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Chapter 2: Board Components Components and Interfaces 2–45 Table 2–35 lists the pin assignments for the DDR3 interface and their corresponding schematic signal names and Stratix V GX pin numbers. Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 1 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description DDR3 Port A Interface (U24, U31) N3 DDR3A_A0 1.5-V SSTL D10 Address bus P7 DDR3A_A1 1.
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2–46 Chapter 2: Board Components Components and Interfaces Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description A2 DDR3A_DQ13 1.5-V SSTL M11 Data bus B8 DDR3A_DQ14 1.5-V SSTL H10 Data bus A3 DDR3A_DQ15 1.5-V SSTL J10 Data bus E3 DDR3A_DQ16 1.5-V SSTL V11 Data bus F7 DDR3A_DQ17 1.5-V SSTL R13 Data bus F2 DDR3A_DQ18 1.
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Chapter 2: Board Components Components and Interfaces 2–47 Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number T21 R2 DDR3B_A7 1.5-V SSTL Description Address bus T8 DDR3B_A8 1.5-V SSTL K16 Address bus R3 DDR3B_A9 1.5-V SSTL U21 Address bus L7 DDR3B_A10 1.5-V SSTL B10 Address bus R7 DDR3B_A11 1.5-V SSTL N16 Address bus N7 DDR3B_A12 1.
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2–48 Chapter 2: Board Components Components and Interfaces Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description D7 DDR3B_DQ24 1.5-V SSTL C16 Data bus C3 DDR3B_DQ25 1.5-V SSTL C15 Data bus C8 DDR3B_DQ26 1.5-V SSTL F14 Data bus C2 DDR3B_DQ27 1.5-V SSTL E14 Data bus A7 DDR3B_DQ28 1.5-V SSTL C13 Data bus A2 DDR3B_DQ29 1.
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Chapter 2: Board Components Components and Interfaces 2–49 Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number K7 DDR3C_CK_N 1.5-V SSTL V20 Description Clock input N J7 DDR3C_CK_P 1.5-V SSTL V21 Clock input P K9 DDR3C_CKE 1.5-V SSTL F22 Clock enable L2 DDR3C_CSN 1.5-V SSTL R21 Chip select E3 DDR3C_DQ0 1.5-V SSTL N17 Data bus F7 DDR3C_DQ1 1.
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2–50 Chapter 2: Board Components Components and Interfaces Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description B7 DDR3C_DQS_N1 1.5-V SSTL H18 Data strobe N byte lane 1 F3 DDR3C_DQS_P2 1.5-V SSTL G19 Data strobe P byte lane 2 G3 DDR3C_DQS_N2 1.5-V SSTL F19 Data strobe N byte lane 2 C7 DDR3C_DQS_P3 1.
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Chapter 2: Board Components Components and Interfaces 2–51 Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 7 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number A28 Data bus Description H7 DDR3D_DQ7 1.5-V SSTL D7 DDR3D_DQ8 1.5-V SSTL F29 Data bus C3 DDR3D_DQ9 1.5-V SSTL G29 Data bus C8 DDR3D_DQ10 1.5-V SSTL G28 Data bus C2 DDR3D_DQ11 1.5-V SSTL F28 Data bus A7 DDR3D_DQ12 1.
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2–52 Chapter 2: Board Components Components and Interfaces Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 8 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number A29 P7 DDR3E_A1 1.5-V SSTL Description Address bus P3 DDR3E_A2 1.5-V SSTL V27 Address bus N2 DDR3E_A3 1.5-V SSTL R27 Address bus P8 DDR3E_A4 1.5-V SSTL T27 Address bus P2 DDR3E_A5 1.5-V SSTL C28 Address bus R8 DDR3E_A6 1.
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Chapter 2: Board Components Components and Interfaces 2–53 Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 9 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number L29 Data bus F2 DDR3E_DQ18 1.5-V SSTL Description F8 DDR3E_DQ19 1.5-V SSTL K30 Data bus H3 DDR3E_DQ20 1.5-V SSTL G32 Data bus H8 DDR3E_DQ21 1.5-V SSTL F32 Data bus G2 DDR3E_DQ22 1.5-V SSTL M30 Data bus H7 DDR3E_DQ23 1.
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2–54 Chapter 2: Board Components Components and Interfaces Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 10 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number B39 Address bus N7 DDR3F_A12 1.5-V SSTL Description T3 DDR3F_A13 1.5-V SSTL T36 Address bus M2 DDR3F_BA0 1.5-V SSTL U36 Bank address bus N8 DDR3F_BA1 1.5-V SSTL B38 Bank address bus M3 DDR3F_BA2 1.
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Chapter 2: Board Components Components and Interfaces 2–55 Table 2–35. DDR3 Interface Pin Assignments, Schematic Signal Names, and Functions (Part 11 of 11) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description A2 DDR3F_DQ29 1.5-V SSTL L32 Data bus B8 DDR3F_DQ30 1.5-V SSTL P34 Data bus A3 DDR3F_DQ31 1.5-V SSTL L33 Data bus F3 DDR3F_DQS_P0 1.5-V SSTL C34 Data strobe P byte lane 0 G3 DDR3F_DQS_N0 1.
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2–56 Chapter 2: Board Components Components and Interfaces Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 2 of 6) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number C5 QDR2A_A4 1.5-V HSTL BA24 Description Address bus C7 QDR2A_A5 1.5-V HSTL BC26 Address bus N5 QDR2A_A6 1.5-V HSTL AW24 Address bus N6 QDR2A_A7 1.5-V HSTL BA25 Address bus N7 QDR2A_A8 1.5-V HSTL AY25 Address bus P4 QDR2A_A9 1.
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Chapter 2: Board Components Components and Interfaces 2–57 Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 3 of 6) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number B9 QDR2A_D17 1.5-V HSTL AH30 Write data bus B3 QDR2A_D18 1.5-V HSTL BD31 Write data bus C3 QDR2A_D19 1.5-V HSTL BC31 Write data bus D2 QDR2A_D20 1.5-V HSTL BA30 Write data bus F3 QDR2A_D21 1.5-V HSTL AR29 Write data bus G2 QDR2A_D22 1.
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2–58 Chapter 2: Board Components Components and Interfaces Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 4 of 6) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number B2 QDR2A_Q18 1.5-V HSTL BD28 Read data bus D3 QDR2A_Q19 1.5-V HSTL AU26 Read data bus E3 QDR2A_Q20 1.5-V HSTL AR27 Read data bus F2 QDR2A_Q21 1.5-V HSTL AP25 Read data bus G3 QDR2A_Q22 1.5-V HSTL AN25 Read data bus K3 QDR2A_Q23 1.
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Chapter 2: Board Components Components and Interfaces 2–59 Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 5 of 6) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number A3 QDR2B_A18 1.5-V HSTL AG17 A10 QDR2B_A19 1.5-V HSTL AK17 Address bus C6 QDR2B_A20 1.5-V HSTL AH19 Address bus B7 QDR2B_BWSN0 1.5-V HSTL BA13 Byte write select A5 QDR2B_BWSN1 1.5-V HSTL AY13 Byte write select A1 QDR2B_CQ_N 1.
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2–60 Chapter 2: Board Components Components and Interfaces Table 2–37. QDR II Interface Pin Assignments, Schematic Signal Names, and Functions (Part 6 of 6) Board Reference Schematic Signal Name I/O Standard Stratix V GX Device Pin Number F2 QDR2B_Q12 1.5-V HSTL AM16 Read data bus G3 QDR2B_Q13 1.5-V HSTL AL16 Read data bus K3 QDR2B_Q14 1.5-V HSTL AL15 Read data bus L2 QDR2B_Q15 1.5-V HSTL AL14 Read data bus N3 QDR2B_Q16 1.5-V HSTL AJ13 Read data bus P3 QDR2B_Q17 1.
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Chapter 2: Board Components Components and Interfaces 2–61 Table 2–39 lists the pin assignments for the Ethernet interface and their corresponding schematic signal names and Stratix V GX pin numbers. All the signal names and directions are relative to the Stratix V GX FPGA. Table 2–39. Ethernet Interface Pin Assignments, Signal Names and Functions (Part 1 of 2) Board Reference (U50) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 8 ENET_GTX_CLK 2.
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2–62 Chapter 2: Board Components Heatsink and Fan Table 2–39. Ethernet Interface Pin Assignments, Signal Names and Functions (Part 2 of 2) Board Reference (U50) Schematic Signal Name I/O Standard Stratix V GX Device Pin Number Description 42 MDI_P3 2.5-V LVCMOS — Media dependent interface 3 43 MDI_N3 2.5-V LVCMOS — Media dependent interface 3 Table 2–40 lists the Ethernet RGMII interface component reference and manufacturing information. Table 2–40.
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Chapter 2: Board Components Power 2–63 Power Distribution System A 19-V DC input from the DC power jack (J2) powers up the development board. Figure 2–10 shows the power distribution system on the development board. Figure 2–10. Power Distribution System 12 V ATX Power LT1374 Switcher 12 V Ideal Diode Mux DC INPUT 14 - 20 V 12 V LTM4601 Switcher 3.3 V Fan MAX II, USB, CLOCKS, CFP, User IO LTC3026 Linear 2.5 V 2.5V_AUX 2.5V_VCCA_PLL LTM4601 Switcher 1.5 V QDR II, DDR3, VCC_IO 1.
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2–64 Chapter 2: Board Components Power Power Measurement There are 11 power supply rails which have on-board voltage and current sense capabilities. These 8-channel differential 24-bit ADC devices and rails are split from the primary supply plane by a low-value sense resistor for the ADC to measure voltage and current. A serial peripheral interface (SPI) bus connects these ADC devices to the MAX II CPLD EPM2210 System Controller. Figure 2–11 shows the block diagram for the power measurement circuitry.
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Chapter 2: Board Components Statement of China-RoHS Compliance 2–65 Table 2–41. Development Board Power Components (Part 2 of 2) Reference Designator Manufacturer Manufacturer Part Number Manufacturer Website Regulator - 100 mA, low noise, LDO U51, U72, U76 micropower regulator, ADJ output, SOT23 Linear Technology LT1761ES5SD#PBF www.linear.com U7, U9, U10, Regulator - 12 A DC/DC µmodule, VIN U11, U12, U13 4.5 V–20 V, VOUT 0.6 V–5 V Linear Technology LTM4601EV#PBF www.linear.
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2–66 100G Development Kit, Stratix V GX Edition Reference Manual Chapter 2: Board Components Statement of China-RoHS Compliance August 2012 Altera Corporation
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Additional Information This chapter provides additional information about the document and Altera. Document Revision History The following table shows the revision history for this document. Date Version August 2012 1.1 January 2012 1.0 Changes ■ New board revision—changed to production silicon. ■ Updated Figure 2–10. ■ Converted document to new frame template and made textual and style changes. Initial release.
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1–2 Additional InformationAdditional Information Typographic Conventions Visual Cue Meaning Indicates variables. For example, n + 1. italic type Variable names are enclosed in angle brackets (< >). For example, and .pof file. Initial Capital Letters Indicate keyboard keys and menu names. For example, the Delete key and the Options menu. “Subheading Title” Quotation marks indicate references to sections in a document and titles of Quartus II Help topics.