User guide
9
1080p Video Design Framework
Altera developed a video design framework that enables the fastest design cycle for video application. The
components of this framework are:
• A library of basic building block video image processing intellectual property (IP) cores designed
for easy plug-and-play type interface
• A low-overhead streaming video interface protocol, which is available as an open standard
• System tools such as SOPC Builder that allow for an automated way of generating control and
arbitration logic
• A suite of HD reference designs that can be used as a starting point for your video datapath
designs
Figure 1 shows the suite of IP cores that are part
of a video image processing suite of IP cores.
This suite provides IP that ranges in complexity
from a color space converter to a polyphase
scaler and motion adaptive de-interlacer.
The Avalon® Streaming interface (ST) video
protocol is designed for sending dvideo and
control data from one video processing block to
the other.
This protocol is open and the specification is
freely downloadable via the web. Using this
specification does not in any way lock you to
Altera® FPGAs, but all the Altera video IP and
video reference designs utilize this interface.
Figure 2 shows how different video functions can
be connected using this protocol. More
information on this protocol is available in the
‘Interface’ section of the Video and Image
Processing Suite User Guide (PDF).
Video systems almost always include an
embedded processor and a memory subsystem to
manage the video frames in the external
memory. The SOPC Builder system tool provided
by Altera greatly simplifies embedded system
design. This tool includes a library of elements
such as soft core processors (Nios® II),
interfaces, memory, bridge, and DSP IP cores. It
also features a connectivity GUI and generator
to automatically wire up arbitrated and
streaming bus systems.
Figure 1 Complete Suite of Video Image Processing IP
Figure 2 Avalon ST Protocol for Video Interfaces and
Avalon Memory Mapped (MM) Protocol for Control Plane
Interfaces