User guide

49
S4 TAI Logic Module for SOC
prototype
DE3 Development System
S2C Inc.
Terasic Technologies
This platform used 2 pcs Altera StratixIV (EP4SE530
/EP4SE820) FPGA, can verify 16.4M ASIC gate
design.
Features
• Up to 66Mbits of FPGA iternal memory
• Up to 2720 embedded 18x8 Multipliers
• One on-board DDR2 SO-DIMM socket
• One on-board DDR3 SO-DIMM socket
• Stackable to meet even larger gate count needs
• Up to 416 dedicated IO per FPGA
• Up to 454 shared nets and IOs for dual FPGA
• 20 user clocks from
 2 oscillator sockets
 3 pairs of differential SMB clock inputs
 3 programmable clock source (1-195MHz)
 12 feedback clocks from any user FPGA
 20 clock sources from J1 connector
Features
• Stratix III 3SL150, 260 or 340
• DDR2 SO-DIMM socket
• 4 push-button switches, 1 DIP switch (x8) and 4
slide switches
• 8 RGB LEDs
• 2 seven-segment displays
• USB Host/Slave Controller with one mini-AB for
host/device and two type A for device
• SD Card socket
• 50MHz onboard oscillator for clock source
• 1 SMA connector for external clock input
• 1 SMA connector for PLL clock output
• Eight 180-pin High Speed Terasic Connectors
(HSTC), where 4 male and 4 female connectors are
on the top and bottom of DE3, respectively.
• Two 40-pin Expansion Headers