User guide

47
A5. Unfortunately, you cannot do the timing
verification on the FPGA prototype as the
timing for ASIC and FPGA are different.
However, doing the functional verification on
the FPGA board is a very effective way to
reduce reiteration of ASIC designs as the most
common reason for ASIC re-spin is the
functional errors.
Altera FPGAs use the same Synopsys Design
Constraints (SDC) used in ASIC design for
FPGA timing constraints. So, the transition
of timing constraint information is smoothly
done between FPGA and ASIC.
Q6. What are the drawbacks in FPGA
prototyping?
A6. Those relying too much on FPGA
prototyping sometimes start skipping the
process of specification writing and logic
simulation.
Without specification sheet the development
can be delayed by going back and forth
between physical verification and small
specification changes again and again, or it
may take more time to debug on the board by
skipping logic simulation. However, these
are not the disadvantage of FPGA prototyping
but it is more of a lack of design flow or project
management.
The FPGA prototyping method is effective in
reducing the total time for development by
operating the verification and design in
parallel, but it requires more human
resources. In the case you choose to employ
the FPGA prototyping, our recommendation is
to consult with design houses with FPGA
design experience.