User guide

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Frequently Asked Questions
Following is the list of questions and answers for
ASIC designers without experience of using
FPGA.
Q1. Do we have to build the FPGA board on
our own?
A1. There are off the shelf ASIC prototyping
board using FPGAs from various vendors.
Please consult with your local Altera
distributors (Altima, Elsene, Cytech, Galaxy)
for details.
If these boards satisfy your specifications and
functions (FPGA density per board,
architecture for scaling the density, I/O types
and speed, memory requirements, etc), it is
highly recommended to use those to reduce
the time and efforts to design, build and verify
the board. If not, you are encouraged to build
your own board.
Q2. How do you do the debugging on the
FPGA?
A2. Unlike in ASICs, you can check the
internal operation of the FPGA while it is in
operation. You will not need oscilloscope or
logic analyzer but you can observe the
waveform of internal signals in operation by
just preparing the FPGA design environment.
However, the debugging with FPGA in
operation is not easier compared with the use
of logic simulator. It is recommended to use
logic simulator for basic and main
functionalities first, and move to FPGA system
verification for smaller bugs.
Q3. As the high level design methodology like
C language becomes common, will the
FPGA prototyping be obsolete?
A3. The high level design methodology like C
language is effective for applications with
frequent update of algorithms as it requires
less man power than RTL design. However,
the simulation speed is usually very slow as
several MHz and the total time needed for
FPGA prototyping is much faster.
It is more realistic to use the high level
verification for algorithm and FPGA
prototyping for system verification. It is also
said that while C language is more
sophisticated for algorithm development, the
experiment on the physical level is very much
important to utilize the human intellectual
activities in the brain.
This is the reason why the FPGA prototyping
method is widely utilized at laboratories for
concept building and proof of concept works.
High level design:
Verify the idea in mind by simulator (no
more evolving of the idea)
FPGA prototyping:
New idea can be found from the results
different from initial expectation
Q4. Do you have to design ASIC and FPGA
differently?
A4. In the case the ASIC design is too big to fit
in one FPGA, you have to partition the design.
Also in the case the performance of FPGA does
not meet requirements, the design need to be
changed to fit the architecture of the FPGA.
Normally the same RTL design can be shared
between ASIC and FPGA.
In the logic emulator you can use the ASIC
design as is, but in reality the emulators use
multiple FPGAs for the hardware part. The
emulators tend to operate at lower
performance than FPGA prototype as
emulators are coupled with gimmicks to
automatically partitioning the design and
improve the ease of debugging.
Q5. Can you do the timing verification?