User guide

Parallel verification
The FPGA prototyping method allows the
hardware design and software verification
simultaneously (hardware-software co-design).
The verification period can be dramatically
reduced by verifying software by functionality on
multiple prototype boards in parallel.
The figure shows how the parallel verification
improves the verification process in the design
flow.
 First Level FPGA Design
The FPGA designers first design the internal
block of FPGA to communicate with software
and external devices so that the software and
board hardware design verification can be
started even before the completion of the
FPGA design. The FPGA designers pass out
the FPGA functional block design to software
engineers after verifying basic functionality by
logic simulation.
 Software Verification
Software designers verify the software using
the FPGA board and FPGA design passed to
them as the result of the process 1. It is
common that the verification is done in
multiple boards by functionality or by the
engineer in parallel. (Parallel software
verification; Parallel board – software
verification)
During this process the FPGA designers
continue the work on the design to add other
functional blocks needed and improve the
design quality of the total FPGA design. As
the design of the FPGA is improved, it is
passed each time to software engineers for
verification. (Parallel logic design – software
verification)
 Specification Change
As the verification of the system continues,
there can be the need to revise the
partitioning between hardware and software
processes, changes in other devices on the
board, I/O specification changes on the FPGA,
etc. As needed, project managers discuss the
changes in specification and work on the
changes to improve the system operation.
Going through this process, the risk of
revisions in the ASIC design by specification
changes can be minimized. (Parallel
specification making – system verification)
 ASIC Design Development
As the design quality of the FPGA design
continues to improve, the ASIC design
development is started in parallel with the
system verification using the FPGA prototype.
The verification using the FPGA prototype
will be continued until the availability of ASIC
engineering sample (ES) as small corner bugs
can be found. (Parallel ASIC design – system
verification)
Hardware Development

Board Development
Software Development
FPGA
Development
First
FPGA
Design
Build multiple
FPGA boards
Software
Design
Verification of
Software
Spec
Change

ASIC Design
Development
FPGA
Redesign &
Verification

ASIC
Tape Out

Build boards
for ASIC
Software
