User guide

44
ASIC Prototyping
Why use FPGAs for ASIC prototyping?
In the modern ASIC design flow, the use of logic simulator software had been a relevant choice of
technique for ASIC designers for long time as the older process ASIC had limited size of the designs.
Also, the lower cost of the mask iterations allowed the designers to spin the design several times per
project.
The traditional design and verification flow is a sequential flow as follows:
(1) Verify the ASIC design using logic simulator and static timing analyzer tools
(2) Develop the evaluation board and ASIC engineering sample (ES)
(3) Verify both hardware and software (system verification) using the outcome of (2)
(4) Redesign and build (2) if any bugs are found because the mask cost was reasonable
The mask cost for the latest ASIC process exceeds multiple million dollars recently, and it is almost
prohibitive to reiterate the ASIC design while the product life cycle is shortening and the workload for
software verification is widening.
The following illustration explains how the introduction of prototyping by FPGA dramatically changes the
ASIC development flow.
Advantages of FPGA prototyping
The verification of design using FPGA can be done at faster speed in operation and in parallel by which
shorter time of total verification can be attained. It is also effective for reducing the risk of ASIC chip
design reiteration by specification change.
Faster operation speed of verification
The prototype design in FPGA can operate in the
speed of as fast as hundreds of MHz. Even the
very expensive emulator costing more than a few
million dollars and the high level verification
tools using C language can attain only a few
MHz at the fastest. The verification speed
using FPGA prototype is predominantly higher
and closer to the speed of the final product.
Moreover, because the test pattern is input
directly from the system, the verification
engineers can skip the process of generating
detailed test bench and expectation values but
the result is observed in the actual system.
This will result in reduction of workload to check
and match the actual output and the expected
results in great deal.
The recommended verification flow in general is:
(1) Design the system architecture by C
language and verify
(2) Verify the logic between function blocks
using logic simulator
(3) Build the FPGA prototype and verify the
system
For instance, it is very difficult to use waveform
for evaluating the picture images by different
algorithms. The verification using the FPGA
prototype enables the engineers actually see the
output images against various image source
data.