User guide

29
High Speed Interface Board Solutions
Transceiver Signal Integrity
Development Kit, Stratix IV GT Edition
Altera Corporation
Altera's Transceiver Signal Integrity Development
Kit, Stratix IV GT Edition enables a thorough
evaluation of transceiver interoperability and
serializer/deserializer (SERDES) signal integrity by
allowing you to evaluate transceiver performance up
to 11.3 Gbps (Altera Stratix IV P4SGX230KF40C2N)
Features
Stratix IV GT development board
EP4S100G2F40I1N
On-board clock oscillators: 50 MHz, 100 MHz,
644.53 MHz, and 706.25 MHz
SMA connectors for supplying an external
differential clock to transceiver reference cloc
DIP and push-button switches
LEDs
LCD
64-MB sync flash memory (primarily to store FPGA
configurations)
Six full-duplex transceiver channels routed to SMA
connectors
All channels support up to 11.3-Gbps data rate
Six full-duplex transceiver channels routed to FCI
Airmax connector
Power measurement circuitry on
transceiver-related supplies
The voltage on all (and only) these rails can be
supplied via banana jacks
Temperature measurement circuitry
RJ-45 jack and 10/100/1000Base-T Ethernet PHY
Backplane drive capability at 6.5 Gbps
Directly connect the transceiver signal integrity
development kit to an FCI backplane (not included)
through the FCI connector header
Couple with a second signal integrity development
kit or FCI daughtercard (not included) for a
complete end-to-end backplane channel analysis
Application GUI
Platform independent
Interfaces to PC via JTAG
Embedded blaster
Quartus II software license is not included and is
not required for kit evaluation
Stratix IV GX FPGA Development Kit
Altera Corporation
The Altera Stratix IV GX FPGA Development Kit
delivers a complete system-level design environment
that includes both the hardware and software needed
to immediately begin developing FPGA designs. With
this PCI-SIG- compliant board and a 1-year license
for Quartus II design software, you can:
Develop and test PCI Express 2.0 (up to x8 lane)
endpoint and rootpoint designs
Develop and test memory subsystems consisting of
DDR3 and/or QDR II+ memory
Build designs capable of migrating to Altera's
low-cost HardCopy IV ASICs.
Features
Stratix IV GX FPGA development board
Stratix IV GX FPGA EP4SGX230KF40C2N
On-board clock oscillators
SMA connectors for external clock input & output
LEDs & LCD display
Push-button & DIP switches
DDR3 SDRAM
512-MByte (64-bit data)
128-MByte (16-bit data)
4-MByte QDR II+ SRAMs (18-bit data) x 2 pcs
64-MByte Sync Flash & 2-MByte SSRAM
PCI Express x8 edge connector
10/100/1000BASE-T Ethernet PHY with RJ-45
connector
Two HSMC connectors
HDMI video output
3G SDI video input and output
Power & Temperature measurement circuitries
Stratix IV GX FPGA Development Kit CD-ROM
Design Examples
Board Update Portal featuring the Nios II
processor web server and remote system update
Board Test System
Complete documentation
Altera's Complete Design Suite DVD
MegaCore IP Library includes PCI Express,
Triple-Speed Ethernet, SDI, and DDR3
High-Performance Controller MegaCore IP cores