User guide
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design software, a common set of IP cores,
sophisticated signal integrity tools, and a variety
of supporting reference designs and design
examples. Learn the software once, then extend
your skills across multiple design platforms.
With the transceiver device and Quartus II
design software, you’ll experience:
• Faster design and compile times
• More efficient system resource
utilization resulting in higher system
integration
• Higher integration with higher density
products
• Optimized core performance, so you can
efficiently close timing on designs and
lower your engineering costs
• The ability to seamlessly connect IP
blocks with a simple, intuitive GUI
Protocol Solutions
Altera® FPGAs and HardCopy® ASICs with integrated transceivers offer a range of data rates to suit all
applications from 600 Mbps to 28 Gbps.
Protocol
Stratix
®
Series
FPGAs
HardCopy
ASICs
Arria
®
Series
FPGAs
Cyclone
®
Series
FPGAs
V GX/GS
V GT
IV GX
IV GT
V GX
IV GX
II GX
IV GX
3G-SDI
10G-SDI
-
-
-
-
10 Gigabit Ethernet XAUI
ASI
-
Basic Mode
CEI-6G/SR/LR
-
-
CEI-11G/SR/LR
-
- - -
CPRI
DDR-XAUI
- -
DisplayPort
-
-
-
-
-
-
-
Fibre Channel
- -
Gigabit Ethernet
GPON
-
HiGig+
-
HiGig2
- -
HyperTransport 3.0
-
-
IEEE 802.3ae 10GBase-R
-
- - -
IEEE 802.3ba 10GBase-KR
-
-
-
-
-
IEEE 802.3ba 40G
-
- - -