User guide

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developed the QDR architecture. QDR is
designed to meet the high-performance needs of
high-speed networking applications.
ZBT SRAM Devices
ZBT SRAM is a synchronous burst SRAM with a
simplified interface that provides higher
bandwidth and efficient bus utilization by
eliminating turnaround cycles and idle cycles
between read and write operations. IDT, Micron,
and Motorola jointly developed the ZBT SRAM
architecture, which is optimized for networking
and telecommunications applications.
External Memory Interface Spec Estimator
Altera’s External Memory Interface Spec Estimator, a parametric tool, allows you to find and compare the
supported external memory interfaces’ highest performance in our FPGA devices. You’ll have the ability to
filter down to specific performances based on your own search specifications, and then compare
performances across FPGA devices side-by-side by filtering the criteria you choose for analysis. The
External Memory Interface Spec Estimator supports DDR3 SDRAM, DDR2 SDRAM, DDR SDRAM,
RLDRAM II, QDRII+ SRAM, and QDRII SRAM interfaces.
The stated performances are the maximum clock
rates supported in Altera's FPGA devices based
on the listed features across supported high
speed memory standards.
The maximum clock rates are only estimates
based on a standalone Altera ALTMEMPHY or
UniPHY and High-Performance Controller II
instance generated with the default PHY and
controller parameters in the MegaCore
®
IP. For
the actual performance of your design, you must
always compile and timing-analyze your
complete design in the Quartus
®
II software.
The External Memory Interface Spec Estimator
replaces the maximum clock rate tables in
Volume 1 Section III: “System Performance
Specifications” of the External Memory
Interfaces Handbook. The FPGA devices
supported by the External Memory Interface
Spec Estimator are the Stratix
®
V, S t r a t i x I V,
Stratix III, Arria
®
II GX, Cyclone
®
IV, and
Cyclone III device families.